• Title/Summary/Keyword: Light-weight cipher algorithm

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The Design of a High-Performance RC4 Cipher Hardware using Clusters (클러스터를 이용한 고성능 RC4 암호화 하드웨어 설계)

  • Lee, Kyu-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.23 no.7
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    • pp.875-880
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    • 2019
  • A RC4 stream cipher is widely used for security applications such as IEEE 802.11 WEP, IEEE 802.11i TKIP and so on, because it can be simply implemented to dedicated circuits and achieve a high-speed encryption. RC4 is also used for systems with limited resources like IoT, but there are performance limitations. RC4 consists of two stages, KSA and PRGA. KSA performs initialization and randomization of S-box and K-box and PRGA produces cipher texts using the randomized S-box. In this paper, we initialize the S-box and K-box in the randomization of the KSA stage to reduce the initialization delay. In the randomization, we use clusters to process swap operation between elements of S-box in parallel and can generate two cipher texts per clock. The proposed RC4 cipher hardware can initialize S-box and K-box without any delay and achieves about 2 times to 6 times improvement in KSA randomization and key stream generation.

Validation Testing Tool for Light-Weight Stream Ciphers (경량 스트림 암호 구현 적합성 검증 도구)

  • Kang Ju-Sung;Shin Hyun Koo;Yi Okyeon;Hong Dowon
    • The KIPS Transactions:PartC
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    • v.12C no.4 s.100
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    • pp.495-502
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    • 2005
  • Cryptographic algorithm testing is performed to ensure that a specific algorithm implementation is implemented correctly and functions correctly. CMVP(Cryptographic Module Validation Program) of NIST in US is the well-known testing system that validates cryptographic modules to Federal Information Processing Standards (FIPS). There is no FIPS-approved stream cipher, and CMVP doesn't involve its validation testing procedure. In this paper we provide validation systems for three currently used light-weight stream ciphers: Bluetooth encryption algorithm E0, 3GPP encryption algorithm A5/3, and RC4 used for WEP and SSL/TLS Protocols. Moreover we describe our validation tools implemented by JAVA programing.

Measurements of Encryption and Decryption Times of AES and LEA Algorithms on an Arduino MCU (아두이노를 이용한 AES와 LEA의 암복호화 속도 측정)

  • Kwon, Yeongjun;Shin, Hyungsik
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.971-977
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    • 2019
  • This paper presents an experimental result showing the encryption and decryption times of the AES and LEA algorithms. AES and LEA algorithms are international and Korean standards for block ciphers, respectively. Through experiments, this paper investigates the applicability of the LEA algorithm for light weight IoT devices. In order to measure the encryption and decryption times, 256-bit and 128-bit secret keys were randomly generated for AES and LEA, respectively. Under our test environment using an Arduino microcontroller, the AES algorithm takes about 45ms for encryption and decryption processes, whereas the LEA algorithm takes about 4ms. Even though processing times of each algorithm may vary much under different implementation and test environments, this experimental result shows that the LEA algorithm can be applied to many light weight IoT devices for security goals.

Area Efficient Implementation of 32-bit Architecture of ARIA Block Cipher Using Light Weight Diffusion Layer (경량화된 확산계층을 이용한 32-비트 구조의 소형 ARIA 연산기 구현)

  • Ryu, Gwon-Ho;Koo, Bon-Seok;Yang, Sang-Woon;Chang, Tae-Joo
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.16 no.6
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    • pp.15-24
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    • 2006
  • Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

Side Channel Attacks on HIGHT and Its Countermeasures (HIGHT에 대한 부채널 분석 및 대응 방법)

  • Kim, Tae-Jong;Won, Yoo-Seung;Park, Jin-Hak;An, Hyun-Jin;Han, Dong-Guk
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.25 no.2
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    • pp.457-465
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    • 2015
  • Internet of Things(IoT) technologies should be able to communication with various embedded platforms. We will need to select an appropriate cryptographic algorithm in various embedded environments because we should consider security elements in IoT communications. Therefore the lightweight block cryptographic algorithm is essential for secure communication between these kinds of embedded platforms. However, the lightweight block cryptographic algorithm has a vulnerability which can be leaked in side channel analysis. Thus we also have to consider side channel countermeasure. In this paper, we will propose the scenario of side channel analysis and confirm the vulnerability for HIGHT algorithm which is composed of ARX structure. Additionally, we will suggest countermeasure for HIGHT against side channel analysis. Finally, we will explain how much the effectiveness can be provided through comparison between countermeasure for AES and HIGHT.