• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.17 no.2
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• pp.59-75
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• 2012

The species composition of plankton is essential to understand the material and energy cycling within marine ecosystem. It also provides the useful information for understanding the properties of marine environments due to its sensitivity to the physicochemical characteristics and variability of water masses. In this study we adopted metagenomics to evaluate eukaryotic plankton species diversity from coastal waters off Busan. Characteristics of water masses at sampling sites is expected to be very complex due to the mixing of various water masses; Nakdong River runoff, Changjiang diluted water (CDW), South Sea coastal water, and Tsushima warm current. 18S rDNA clone libraries were constructed from surface waters at the three sites off Busan. Clone libraries revealed 94 unique phylotypes from 370 clones; Dinophyceae(42 phylotypes), Ciliophora(15 phylotypes), Bacillariophyta(7 phylotypes), Chlorophyta(2 phylotypes), Haptophyceae(1 phylotype), Metazoa(Arthropoda( 17 phylotypes), Chaetognatha(1 phylotypes), Cnidaria(2 phylotypes), Chordata(1 phylotype)), Rhizaria (Acantharea(2 phylotypes), Polycystinea(1 phylotype)), Telonemida(1 phylotype), Fungi(2 phylotypes). The difference in species diversity at the closely located three sites off Busan may be attributed to the various physicochemical properties of water masses at these sites by the mixture of water masses of various origins. Metagenomic study of species composition may provide useful information for understanding marine ecosystem of coastal waters with various physicochemical properties in the near feature.

• Journal of Plant Biotechnology
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• v.47 no.3
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• pp.218-226
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• 2020

This report describes methods for selecting informative single nucleotide polymorphisms (SNPs), and the development of an online Solanaceae genome database, using 234 tomato resequencing data entries deposited in the NCBI SRA database. The 126 accessions of Solanum lycopersicum, 68 accessions of Solanum lycopersicum var. cerasiforme, and 33 accessions of Solanum pimpinellifolium, which are frequently used for breeding, and some wild-species tomato accessions were included in the analysis. To select tag-SNPs, we identified 29,504,960 SNPs in 234 tomatoes and then separated the SNPs in the genic and intergenic regions according to gene annotation. All tag-SNP were selected from non-synonymous SNPs among the SNPs present in the gene region and, as a result, we obtained tag-SNP from 13,845 genes. When there were no non-synonymous SNPs in the gene, the genes were selected from synonymous SNPs. The total number of tag-SNPs selected was 27,539. To increase the usefulness of the information, a Solanaceae genome database website, TGsol (http://tgsol. seeders.co.kr/), was constructed to allow users to search for detailed information on resources, SNPs, haplotype, and tag-SNPs. The user can search the tag-SNP and flanking sequences for each gene by searching for a gene name or gene position through the genome browser. This website can be used to efficiently search for genes related to traits or to develop molecular markers.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• 대한공업교육학회지
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• v.42 no.1
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• pp.140-159
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• 2017

The purpose of this research was to collect and select the theses and articles of the STEAM education in domestic and to analyze a research status by the review, then to suggest a direction of the further research in technology education. The objects of this research were the theses and articles of the STEAM education in domestic published from January 2007 to June 2016. I collected the theses and articles by using the search engine of the Korean Academic Information Service, the Korea Education and Research Information Service, the National Assembly Digital Library, and finally selected 821 theses and articles for the objects. I analyzed the theses and articles by verifying their subjects, abstracts and contents, and applied the analysis framework developed in advance. I used the frequency analysis, the cross analysis to analyze the datas statistically. Also, I used SPSS 18.0 program. Drawing on the finding of this research, major conclusions of this research were as follows. First, the researches of the STEAM education in domestic had been studied numerously from 2012 to 2015, but it has been decreased since 2016. Second, the researches of the STEAM education in domestic have been studied numerously for the development of the educational program and the instructional source. Third, the research objects of the STEAM education in domestic have been studied numerously for elementary school, middle school and high school in a row. Forth, the researches of the STEAM education in domestic have been focused numerously on a science. Fifth, the researches of the STEAM education in domestic have been concerned mainly about the creativity effect among other educational effects.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.876-884
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• 2014

A hardware design of LDPC decoder which is based on the improved normalized min-sum(INMS) decoding algorithm is described in this paper. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. The decoding function unit(DFU) which is a main arithmetic block is implemented using sign-magnitude(SM) arithmetic and INMS decoding algorithm to optimize hardware complexity and decoding performance. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 100 MHz clock has 284,409 gates and RAM of 62,976 bits, and it is verified by FPGA implementation. The estimated performance depending on code rate and block length is about 82~218 Mbps at 100 MHz@1.8V.

• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.204-214
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• 2013

Recently various research have been conducted relating to the implementation of signal processing or communication system by software using the massively parallel processing capability of the GPU. In this work, we focus on reducing software simulation time of 2K/8K FFT in DVB-T by using GPU. we estimate the processing time of the DVB-T system, which is one of the standards for DTV transmission, by CPU. Then we implement the FFT processing by the software using the NVIDIA's massively parallel GPU processor. In this paper we apply stream process method to reduce the overhead for data transfer between CPU and GPU, coalescing method to reduce the global memory access time and data structure design method to maximize the shared memory usage. The results show that our proposed method is approximately 20~30 times as fast as the CPU based FFT processor, and approximately 1.8 times as fast as the CUFFT library (version 2.1) which is provided by the NVIDIA when applied to the DVB-T 2K/8K mode FFT.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.756-771
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• 2003

Digital Video Library System which manages a large amount of multimedia information requires efficient and effective retrieval methods. In this paper, we propose and implement a new video search and retrieval algorithm that compares the query video shot with the video shots in the archives in terms of foreground object, background image, audio, and its context. The foreground object is the region of the video image that has been changed in the successive frames of the shot, the background image is the remaining region of the video image, and the context is the relationship between the low-level features of the adjacent shots. Comparing these features is a result of reflecting the process of filming a moving picture, and it helps the user to submit a query focused on the desired features of the target video clips easily by adjusting their weights in the comparing process. Although the proposed search and retrieval algorithm could not totally reflect the high level semantics of the submitted query video, it tries to reflect the users' requirements as much as possible by considering the context of video clips and by adjusting its weight in the comparing process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.344-354
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of $1024{\times}1024$, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using $0.35{\mu}m$ CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.