• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.21-30
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• 2002

According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.3-3
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• 1995

Plastic IC encapsulation utilizing lead on chip(LOC) die attach technique allows higher device density per unit package area, and faster current speed and easter leadframe design. Nevertheless, since the top surface of the chip is directly attached to the area of the leadframe with a double-sided adhesive tape in the LOC package, it tends to be easily damaged by the leadframe, leading to limitation in its utilization. In this work, it is detailed how the damage of the chip surface occurs, and it is influenced and improved by the LOC construct.

• Journal of the Korean Society for Heat Treatment
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• v.5 no.3
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• pp.165-170
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• 1992

The chip controls are investigated experimentally for the purpose of estimating cutting ability of hardened steel. In this experiment, hardened STD11 steel ($HR_c$ 60) is turned with carbide tool M20 under various cutting conditions and with several tool shapes. The main results obtained are as follows : 1) Cutting conditions of cutting speed 45m/min. feed 0.09-0.13 rev. depth of cut 0.4-0.6 are recommended for the chip excluding. 2) In case that the feed becomes larger and a lead angle of cutting tool becomes smaller, the chip excluding becomes easier. 3) It is confirmed that frank wear and crator wear on the cutting tool appear severely from about 10 min. after cutting start and chip excluding get worse.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.6
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• pp.175-181
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• 2013

The primary element of machining automation is to maximize the utilization of machine tools, which determines the output and lead-time. In particular, 95% of raw materials for wing ribs are cut into chips and 0.6 ton of chips are generated every hour from each machine tool. In order to verify the chip recycling system that controls the chips from the machines in five-axis FMS line, a simulation of the virtual model is constructed using the QUEST simulation program. The optimum speed of the chip conveyor and its operating conditions that directly affect the efficiency of the FMS line are presented including the chip conveyor speed, the maximum capacity of the hopper, and the number of chip compressors.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.19-24
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• 2000

To make stacked chip packages far high-density packaging of memory chips used in workstations or PC severs, several lead-frames are to be connected vertically. Fer this purpose. Sn or Sn/Ag were electrochemically deposited on Cu lead-frames and their microstructures were examined by XRD and SEM. Then, two specimens were annealed at $250^{\circ}C$ for 10 min. and pressed to be joined. The shear stresses of joined lead-frames were measured fur comparison. In the case of Sn only, $Cu_3Sn$ was formed by the reaction of Sn and Cu lead-frames. In the case of Sn/Ag, besides $Cu_3Sn$. $Ag_3Sn$ was formed by the reaction of Sn and Ag. Compared to joined specimens made from Sn only, those made from Sn/Ag showed 1.2 times higher shear stress. This was attributed to the $Ag_3Sn$ phase formed at the joined interface.

• Proceedings of the KWS Conference
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• 2002.05a
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• pp.269-271
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• 2002

• Tribology and Lubricants
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• v.21 no.2
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• pp.71-76
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• 2005

This paper compares of mechanical tensile properties of 6 kinds of copper foil. The beam lead made with copper foil. Different from other package type such as plastic package, Chip Size Package has a reliability problem in beam lead rather than solder joint in board level. A new tensile loading system was developed using voice-coil actuator. The new tensile loading system has a load cell with maximum capacity of 20 N and a non-contact position measuring system based on the principle of capacitance micrometry with 0.1nm resolution for displacement measurement. Strain was calculated from the measured displacement using FE analysis. The comparison of mechanical properties helps designer of package to choose copper for ensuring reliability of beam lead in early stage of semiconductor development.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.35-40
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• 2000

MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.185-192
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• 1989

It is shown that GaAs/GaAs stripe Roof-Top-Reflector LD is better than cleaved mirror LD by numerical analysis. And surface light emitting device is developed by LPE melt-back growth, which is of good controllability for OEIC. OEIC transmitter using RTR LD structured device and FET has been made and modulated, expected to show good modulation characteristics after solving process problem. Beam-Lead LD mounted on Si carrier has been made and shows low heat-resistance and so long life and good characteristics of LD.