• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.213-216
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• 2001

Key frame extraction is an important method of summarizing a long video. This paper propose a technique to automatically extract several key frames representative of its content from video. We use the color layout descriptor to select key frames from video. For selection of key frames, we calculate similarity of color layout features extracted from video, and extract key frames using similarity. An important aspect of our algorithm is that does not assume a fixed number of key frames per video; instead, it selects the number of appropriate key frames of summarizing a long video Experimental results show that our method using color layout descriptor can successfully select several key frames from a video, and we confirmed that the processing speed for extracting key frames from video is considerably fast.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.14-21
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• 1985

In this paper, a new pitch extraction method, the area comparison method, is proposed. By the speech production model, the area of the first peak on a pitch interval of speech signals is emphasized. By using the above characteristics, this method have more advantages than the others for pitch extraction. The defective decision caused by an impulsive noise is minimized and the pre-filtering is not necessary for this rr ethos, because the integration of signals takes place in the process.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.979-982
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• 1999

A new accurate as well as efficient multi-layer interconnect capacitance extraction method is presented. Since Multi-layer interconnects is too complicated to directly extract capacitances, it is simplified with virtual ground concept. To make the structure tractable, the shielding effects should be separately determined. Since the electric field shielding effects, and the solid-ground-based capacitance matrices can be readily determined from the layout geometry, the accurate as well as efficient quasi-3D capacitances concerned with an objective line can be readily determined. In order to demonstrate its efficiency and accuracy, the parameters and circuit responses were benchmarked with 3D-field-solver-based results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1081-1090
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• 1988

A series of procedures using image processing techniques is presented for extracting layout information fast and automatically from chip images. CIF (caltech intermediate form) is chosen for representing such information. First, line-edges are extracted using a line-edge detector. Then, thinning and noise removal procedures follow. Subsequent procedures are vertex extraction and vertex grouping. Finally, CIF is extracted from the coordinates of the grouped vertices. In this paper, the final process is applied to only metal layer. In experiments, this processing scheme is shown to be very effective in extracting CIF.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.10
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• pp.4072-4091
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• 2015

A separation of text and non-text elements plays an important role in document layout analysis. A number of approaches have been proposed but the quality of separation result is still limited due to the complex of the document layout. In this paper, we present an efficient method for the classification of text and non-text components in document image. It is the combination of whitespace analysis with multi-layer homogeneous regions which called recursive filter. Firstly, the input binary document is analyzed by connected components analysis and whitespace extraction. Secondly, a heuristic filter is applied to identify non-text components. After that, using statistical method, we implement the recursive filter on multi-layer homogeneous regions to identify all text and non-text elements of the binary image. Finally, all regions will be reshaped and remove noise to get the text document and non-text document. Experimental results on the ICDAR2009 page segmentation competition dataset and other datasets prove the effectiveness and superiority of proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.805-813
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• 2002

Document image should be classified into detailed regions as text, picture, table and etc through the geometric layout analysis if paper documents can be converted automatically into electronic documents. However, complexity of the document layout and variety of the size and density of a picture are the reason to make it difficult to analyze the geometric layout of the document images. In this paper, we propose the method which have a better performance of the region segmentation and classifications, and the line extraction in the table region than the commercial softwares and previous methods. The proposed method can segment the document into detailed regions by using connected components method even if its layout is complex. This method also classifies texts and pictures by using separable median filter even. Though their size and density are diverse, In addition, this method extracts the lines from the table adapting one dimensional median filter to the each horizontal and vertical direction, even though lines are deformed or texts attached to them.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1525-1527
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• 1987

This paper describe the KUIC-CEX, an automated CMOS layout verification program which extracts circuit connectivity, MOSFET dimensions, and parasitic capacitance for CIF(1) file. In the KUIC-CEX, Bitmap approach(2, 3) is used for basic operation. Since the output of this program is the Input file format of PSPICE, we can easily verify the layout of circuit. This program is written in C language.

• Journal of Creative Information Culture
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• v.5 no.2
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• pp.145-156
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• 2019

In this study, we have developed and evaluated an information extracting module based on the named entity recognition technique. For the given purpose in this paper, the module was designed to apply to the problem dealing with extraction of postal address information from arbitrary documents without any prior knowledge on the document layout. From the perspective of information technique practice, our approach can be said as a probabilistic n-gram (bi- or tri-gram) method which is a generalized technique compared with a uni-gram based keyword matching. It is the main difference between our approach and the conventional methods adopted in natural language processing that applying sentence detection, tokenization, and POS tagging recursively rather than applying the models sequentially. The test results with approximately two thousands documents are presented at this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.101-108
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• 2004

A 16-bit adiabatic ALU(arithmetic logic unit) is designed. A simplified four-phase clock generator is also designed to provide supply clocks for the adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on ECRL (efficient charge recovery logic) using a 0.35${\mu}{\textrm}{m}$ CMOS technology. The post-layout simulation results show that the power consumption of the adiabatic ALU including supply clock generator is reduced by a factor of 1.15-1.77 compared to the conventional CMOS ALU with the same structure.