• KSCE Journal of Civil and Environmental Engineering Research
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• v.42 no.2
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• pp.257-261
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• 2022

Additive manufacturing (AM, also known as 3D printing) applied to the construction industry is implemented and verified for various effects since advantages such as high design freedom, improving worker safety, and predictable construction period. However, due to the low maturity compared to the existing technology, studies are underway to solve new problems that occur in the overall of AM technology. In this paper, we confirm the effect of low construction surface flatness on the stacked features in the process of on-site AM construction. In particular, unstable AM features are determined through quantitative analysis by laser scanning, and a construction strategy is proposed for the surface flattening.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2004.10a
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• pp.184-187
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• 2004

The sheet parts are formed with dies conventionally. But this conventional forming process is not suited to small volume and varied production for the reason of high cost. For the solution of this problem, a new forming process, which is called CNC incremental sheet forming, is being introduced. This process can form sheet parts without die, and is very well suited to small volume and varied production in space flight and automobile. In this paper, dieless CNC forming system based on a machining center is developed. A special device to grasp and pull the blank sheet built in the machining center and tool path generation S/W from STL file of 3-D model are developed. Several sheet parts are incrementally formed to verify the effectiveness of the developed system.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.73-82
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• 2003

Recently, PWB(Printed Wiring Board) has been recognized in the field of microelectronic package as core technology for designing or manufacturing. PWB is the structure stacked by several materials with different thermophysical properties, which shows the different CTEs(Coefficient or Thermal Expansions) during the fabrication process and causes a lot of defects such as warpage, shrinkage, dimension, etc. Thermal deformation of PWB is affected mainly by the volume change of solder-resist among fabrication parameters. Therefore, thermal deformation of PBGA and CSP consisting of 2 layers and 4 layers was studied with solder-resist process. When over 30% in volume fraction of solder-resist, thermal deformation of 2-layered PWB was min. 40% higher than that of 4-layered PWB because 4-layered PWB contained the layer with high toughness such as prepreg, which counterbalanced the thermal deformation of solder-resist. Otherwise, when below 30%, PWB showed similar thermal deformation without regard to layers and design.

• Korean Journal of Materials Research
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• v.31 no.12
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• pp.710-718
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• 2021

Recently, due to high theoretical capacitance and excellent ion diffusion rate caused by the 2D layered crystal structure, transition metal hydroxides (TMHs) have generated considerable attention as active materials in supercapacitors (or electrochemical capacitors). However, TMHs should be designed using morphological or structural modification if they are to be used as active materials in supercapacitors, because they have insulation properties that induce low charge transfer rate. This study aims to modify the morphological structure for high cycling stability and fast charge storage kinetics of TMHs through the use of nickel cobalt hydroxide [NiCo(OH)₂] decorated on nickel foam. Among the samples used, needle-like NiCo(OH)₂ decorated on nickel foam offers a high specific capacitance (1110.9 F/g at current density of 0.5 A/g) with good rate capability (1110.9 - 746.7 F/g at current densities of 0.5 - 10.0 A/g). Moreover, at a high current density (10.0 A/g), a remarkable capacitance (713.8 F/g) and capacitance retention of 95.6% after 5000 cycles are noted. These results are attributed to high charge storage sites of needle-like NiCo(OH)₂ and uniformly grown NiCo(OH)₂ on nickel foam surface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.275-280
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• 2001

Recently, the trends of industrial products grow more miniaturization, variety and mass production. Micro drilling which take high precision in cutting work is requested more micro hole and high speed working. Especially, Micro deep hole drilling is becoming more important in a wide spectrum of precision production industries, ranging from the production of automotive fuel injection nozzle, watch and camera parts, medical needles, and thick multi-layered Printed Circuit Boards(PCB) that are demanded for very high density electric circuitry. This paper shows the tool monitoring results of micro drill with tool dynamometer. And additionally, microscope with built-in monitor inspection show the relationship between burr in workpiece and chip form of micro drill machining.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• Steel and Composite Structures
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• v.49 no.4
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• pp.361-380
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• 2023

A size dependent bending behavior of piezoelectrical flexoelectric layered perforated functionally graded (FG) composite nanobeam rested on an elastic foundation is investigated analytically. The composite beam is composed of regularly cutout FG core and two piezoelectric face sheets. The material characteristics is graded through the core thickness by power law function. Regular squared cutout perforation pattern is considered and closed forms of the equivalent stiffness parameters are derived. The modified nonlocal strain gradient elasticity theory is employed to incorporate the microstructure as well as nonlocality effects into governing equations. The Winkler as well as the Pasternak elastic foundation models are employed to simulate the substrate medium. The Hamiltonian approach is adopted to derive the governing equilibrium equation including piezoelectric and flexoelectric effects. Analytical solution methodology is developed to derive closed forms for the size dependent electromechanical as well as mechanical bending profiles. The model is verified by comparing the obtained results with the available corresponding results in the literature. To demonstrate the applicability of the developed procedure, parametric studies are performed to explore influences of gradation index, elastic medium parameters, flexoelectric and piezoelectric parameters, geometrical and peroration parameters, and material parameters on the size dependent bending behavior of piezoelectrically layered PFG nanobeams. Results obtained revealed the significant effects both the flexoelectric and piezoelectric parameters on the bending behavior of the piezoelectric composite nanobeams. These parameters could be controlled to improve the size dependent electromechanical as well as mechanical behaviors. The obtained results and the developed procedure are helpful for design and manufacturing of MEMS and NEMS.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.1 s.94
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• pp.95-107
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• 1999

The design models of a new product in general are created using clay models or wooden mock-ups. The reverse engineering(RE) technology enables us to quickly create the CAD model of the new product by capturing the surface of the model using laser digitizers or coordinate measuring machines. Rapid prototyping (RP) is another technology that can reduce the product development time by fabricating the physical prototype of a part using a layered manufacturing technique. In reverse engineering process, however, the digitizer generates an enormous amount of point data, and it is time consuming and also inefficient to create surfaces out of these data. In addition, the surfacing operation takes a great deal of time and skill and becomes a bottleneck. In rapid prototyping, a faceted model called STL file has been the industry standard for providing the CAD input to RP machines. It approximates the CAD model of a part using many planar triangular patches and has drawbacks. A novel procedure that overcomes these problems and integrates RE with RP is proposed. Algorithms that drastically reduce the point clouds data have been developed. These methods will facilitate the use of reverse engineered geometric data for rapid prototyping, and thereby will contribute in reducing the product development time.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.2
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• pp.110-113
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• 2008

Embedded capacitor technology is one of the effective packing technologies for further miniaturization and higher performance of electric packaging system. In this paper, the embedded capacitors were simulated and fabricated in 8-layered printed circuit board employing standard PCB processes. The composites of barium titanante($BaTiO_3$) powder and epoxy resin were employed for the dielectric materials in embedded capacitors. Theoretical considerations regarding the embedded capacitors have been paid to understand the frequency dependent impedance behavior. Frequency dependent impedance of simulated and fabricated embedded capacitors was investigated. Fabricated embedded capacitors have lower self resonance frequency values than that of the simulated embedded capacitors due to the increased parasitic inductance values. Frequency dependent capacitances of fabricated embedded capacitors were well matched with those of simulated embedded capacitors from the 100MHz to 10GHz range. Quality factor of 20 was observed and simulated at 2GHz range in the 10 pF embedded capacitors. Temperature dependent capacitance of fabricated embedded capacitors was presented.