• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.430-430
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• 2010

MICC 방법으로 제작된 TFT는 large grain과 그에 따른 grain boundary의 감소로 인하여여, 소자의 전기적 특성을 좋게 할 수 있다. 본 연구에서는 bi-layer channel의 large grain size TFT를 제작하여 소자의 전기적 특성을 비교하였다. Channel의 width / length의 크기는 각 각의 경우 $7/5{\times}2$, $10/5{\times}2$, $15/5{\times}2$ (${\mu}m$)로 하였다. 소자의 성능 측정 결과 Field-effect mobility의 경우에는 channel width가 증가할 수록 감소하는 경향성을 나타내었으며, Threshold voltage의 경우에는 조금 감소하는 경향성은 있었으나 변화의 폭이 매우 작았다. Output characteristics 의 경우에는 모든 set에서 좋은 saturation 특성을 보였다. 이것은 current croding이 없었다는 것을 의미하는데, 큰 grain size로 인한 효과로 해석 할 수 있다. 본 연구에서는 bi-layer channel에서 corner effect에 중점을 두어 소자의 전기적 특성 변화에 대하여 논하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.367-367
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• 2010

Electrical characteristics of Large-grain silicon with Ni-induced crystallization which gate insulator is made of 80 nm $SiO_2$ and 20 nm SiNx was fabricated and measured with different channel widths, channel length fixed $10{\mu}m$. Focusing on the changes of channel widths from $4{\mu}m$ to $40{\mu}m$. Field-effect mobility decreased from 111.30 to $94.10\;cm^2/V_s$ when the channel widths increased. Still threshold voltage was almost similar with -1.06V.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.429-429
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• 2010

TFT 제조 방법 중 LTPS (Low Temperature Polycrystalline Silicon)는 저온과 저비용 등의 이점으로 인하여 flat panel display 제작에 널리 사용된다. 이동도와 전류 점멸비 등에서 이점을 가지는 ELA(Excimer Laser Annealing)가 널리 사용되고 있지만, 이 방법은 uniformity 등의 문제점을 가지고 있다. 이를 극복하기 위한 방법으로 MICC(Metal Induced Capping Crystallization)이 사용되고 있다. 이 방법은 $SiN_x$, $SiO_2$, SiON등의 capping layer를 diffusion barrier로 위치시키고, Ni 등의 금속을 capping layer에 도핑 한 뒤, 다시 한번 열처리를 통하여 a-Si에 Ni을 확산시키킨다. a-Si 층에 도달한 Ni들이 seed로 작용하여 Grain size가 매우 큰 film을 제작할 수 있다. 채널의 grain size가 클 경우 grain boundary에 의한 캐리어 scattering을 줄일 수 있기 때문에 MIC 방법을 사용하였음에도 ELA에 버금가는 소자의 성능과 안정성을 얻을 수있었다. 본 연구에서는 large grain TFT의 Gate bias stress에 따른 소자의 안정성 측정 및 분석에 목표를 두었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.146-146
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• 2010

Electrical properties of Large-grain-size TIT with 7/7 ${\mu}m$ channel width and length which gate insulator is made of 20nm $SiO_2$ and 80nm $SiN_x$. was fabricated and measured with Large-grain-size technic(MICC) and compared to ELA technic's data. The field-effect mobility was decreased from 106.78 to $88.74\;cm^2$/Vs and threshold voltage also decreased from -1.8382 to -0.9529 V, when TFT process is changed from ELA technic to MICC technic. Subthreshold swing, also, increased from 0.22 to 0.32 V/dec and $I_{on/off}$ ratio decreased from $1.12{\times}10^8$ to $5.75{\times}10^7$.

• ETRI Journal
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• v.29 no.1
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• pp.45-49
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• 2007

The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.163-166
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• 2002

We studied the growth of large-grain pentacene film by organic vapour phase deposition. The optimizations of the growth of pentacene are carried out by varying the gas pressure in the reactor and substrate temperature. We found that the grain size depends strongly on the gas pressure in the reactor. The grain size of $20{\mu}m$ has been obtained at the gas pressure of 200 Torr. The film was found to be strongly (001) oriented and its grain size decreases with decreasing the gas pressure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.111-114
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• 2008

We studied the influence of nanocrystalline silicon (nc-Si) thin film thickness on top gate nc-Si thin film transistor (TFT) fabricated at $180^{\circ}C$. The nc-Si thickness affects the characteristics of nc-Si TFT due to the nc-Si growth similar to a columnar. As the thickness of nc-Si increases from 40 nm to 200 nm, the grain size was increased from 20 nm to 40 nm. Having a large grain size, the thick nc-Si TFT surpasses the thin nc-Si TFT in terms of electrical characteristics such as field effect mobility. The channel resistance was decreased due to growth of the grain. We obtained the experimental results that the field effect mobility of the fabricated devices of which nc-Si thickness is 60, 90 and 130 nm are 26, 77 and $119\;cm^2/Vsec$, respectively. The leakage current, however, is increased from $7.2{\times}10^{-10}$ to $1.9{\times}10^{-8}\;A$ at $V_{GS}=-4.4\;V$ when the nc-Si thickness increases. It is originated from the decrease of the channel resistance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.62-62
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• 2009

Electrical properties of SGS-TFT with 5/5 ${\mu}m$ channel width and length which gate insulator is made of 20nm $SiO_2$ and 80nm $SiN_x$ was fabricated and measured at various temperatures. The field-effect mobility was decreased from 86.25 to 80.42 $cm^2/Vs$ and threshold voltage also decreased from -1.5792 to -1.0492 V, when temperature is increased from room temperature to $100^{\circ}C$. Subthreshold swing, also, increased from 0.3212 to 0.4818 V/dec and $I_{on/off}$ ratio decreased from $5.05{\times}10^7$ to $6.93{\times}10^5$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.368-368
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• 2010

Using TFTs crystallized by MICC and ELA, electron mobility and threshold voltage were measured according to various substrate temperature from $-40^{\circ}C$ to $100^{\circ}C$. Basic curve, $V_G-I_D$, is also measured under various stress time from 1s to 10000s. Consequently, due to the passivation effect and number of grains, mobility of MICC is varied in the range of -8% ~ 7.6%, while that of ELA is varied from -11.04% ~ 13.25%. Also, since $V_G-I_D$ curve is dominantly affected by grain size, active layer interface, the graph remained steady under the various gate bias stress time from 1s to 10000s. This proves the point that MICC can be alternative technic to ELA.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.254-255
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• 2012

Interest in nano-crystalline silicon (nc-Si) thin films has been growing because of their favorable processing conditions for certain electronic devices. In particular, there has been an increase in the use of nc-Si thin films in photovoltaics for large solar cell panels and in thin film transistors for large flat panel displays. One of the most important material properties for these device applications is the macroscopic charge-carrier mobility. Hydrogenated amorphous silicon (a-Si:H) or nc-Si is a basic material in thin film transistors (TFTs). However, a-Si:H based devices have low carrier mobility and bias instability due to their metastable properties. The large number of trap sites and incomplete hydrogen passivation of a-Si:H film produce limited carrier transport. The basic electrical properties, including the carrier mobility and stability, of nc-Si TFTs might be superior to those of a-Si:H thin film. However, typical nc-Si thin films tend to have mobilities similar to a-Si films, although changes in the processing conditions can enhance the mobility. In polycrystalline silicon (poly-Si) thin films, the performance of the devices is strongly influenced by the boundaries between neighboring crystalline grains. These grain boundaries limit the conductance of macroscopic regions comprised of multiple grains. In much of the work on poly-Si thin films, it was shown that the performance of TFTs was largely determined by the number and location of the grain boundaries within the channel. Hence, efforts were made to reduce the total number of grain boundaries by increasing the average grain size. However, even a small number of grain boundaries can significantly reduce the macroscopic charge carrier mobility. The nano-crystalline or polymorphous-Si development for TFT and solar cells have been employed to compensate for disadvantage inherent to a-Si and micro-crystalline silicon (${\mu}$-Si). Recently, a novel process for deposition of nano-crystralline silicon (nc-Si) thin films at room temperature was developed using neutral beam assisted chemical vapor deposition (NBaCVD) with a neutral particle beam (NPB) source, which controls the energy of incident neutral particles in the range of 1~300 eV in order to enhance the atomic activation and crystalline of thin films at room temperature. In previous our experiments, we verified favorable properties of nc-Si thin films for certain electronic devices. During the formation of the nc-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. The more resent work on nc-Si thin film transistors (TFT) was done. We identified the performance of nc-Si TFT active channeal layers. The dependence of the performance of nc-Si TFT on the primary process parameters is explored. Raman, FT-IR and transmission electron microscope (TEM) were used to study the microstructures and the crystalline volume fraction of nc-Si films. The electric properties were investigated on Cr/SiO2/nc-Si metal-oxide-semiconductor (MOS) capacitors.