• Journal of Institute of Control, Robotics and Systems
• /
• v.7 no.12
• /
• pp.1009-1014
• /
• 2001

The ladder diagram (LD) for programmable logic controllers (PLCs) ar responsible for much important roles in advance industrial automation. As automated systems become more complex the design procedures of the system become more difficult as well. Hence. the design automation issues based on discrete event models(DEMs) are receiving more attention. One of the popular ways of tackling these problems is employing Petri nets. In this paper, we use the modified automation Petri net(MAPN) to model the manufacturing system and the modified token passing logic (MTPL) method conversion (ECC) algorithm based on the MAPN and the MTPL Finally, an example of the manufacturing system is provided to illustrate the proposed ECC algorithm.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2006.05a
• /
• pp.462-466
• /
• 2006

In industrial control system used by Programmable Logic Controller(PLC), Ladder Diagram(LD) is the about widely utilized and plays an important role in industrial control system. But recently, the study about Sequential Function Chart(SFC) is performed actively. When we program by SFC, generally, we design one routine from start to end. This method is difficult to design, and we often make mistakes. In this paper, we propose the method that we compose each sub-system after we design each sub-system and we analysis the difference of the method used this paper from conventional method.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.13-26
• /
• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• The KIPS Transactions:PartD
• /
• v.11D no.2
• /
• pp.415-422
• /
• 2004

Automation systems improve the productivity of works which relate to product design, facilities management, fault processing and quality evaluation. In these systems, the description language for monitoring and control process is called new control language. These are five flow control languages : IL, ST, FBD, SFC and LD. IL and ST are based on left form. FBD, SFC and LD are based on graphic form. Generally, a software which monitors and controls a system is allowed to use just one flow control language. It is impossible to use more than two languages for simulation in the same system environment. In this paper, we analyzed the characteristics of flow control languages and the process of programming in the legacy system. In addition, for the Integrated processing of languages, we propose Extended ST based on the high-level ST language. Based on this research, we implement a graphical language editor and EST-IL convertor. The graphical language editor makes sequence rules, and converts graphical language into EST. EST-IL convertor has a function to convert EST into IL which is similar to assembly language. As the result of this paper, we present a scheme which integrates all the flow control language processing based on IL.

• IE interfaces
• /
• v.21 no.3
• /
• pp.294-301
• /
• 2008

Agile and flexible manufacturing systems make it mandatory that a control program should have features such as agility, flexibility, and reusability in order to run manufacturing unit smoothly. PLCs are the most frequently used control program in manufacturing systems. PLC programs are mostly programmed by subcontraction, which makes correction of code very difficult. As a result, it may cause delay during down time and ramp up time which leads to big loss of revenue and goodwill. To prevent delay during the times, this paper proposes systematic process analysis and application method for programmable logic controller like LLD (Ladder Logic Diagram). The proposed method uses modified human-error investing techniques for documentation and transforming technique to program LLD from the documentation. Furthermore, this paper demonstrates an example of piston mechanism to explain the proposed method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.3
• /
• pp.105-110
• /
• 2005

Programmable Logic Controller(PLC) is the most widely utilized among many sorts of existing controller for the design of factory automation control system, and study about a PLC language is peformed actively. In this paper, we proposed the encoding module that we increase input points when increased of the input machine which is going to control it in the FA design that used PLC. Input point is going to be extended with 2-3 points in the state that cannot equip input unit in basic base any more. Then an extension base, a power supply, an extension cable and an output nit must be equipped particularly. Then a cost must be added very much. This paper proposed the encoding module which extended an input in a small quantity, and we confirmed a feasibility through a simulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.6
• /
• pp.1260-1268
• /
• 2005

Ladder Diagram(LD) is the most extensively used among PLC standard language for the design of control system. But LD has the disadvantages for data processing and maintenance. On the other hand, the Sequential Function Chart(SFC) graphic language is very powerful for describing the sequential logic control algorithm. SFC is based on flow chart, so control flow understanding is very easy and divergence can possible improving its ability. In this paper, we propose the efficient management elevator system using the action qualifiers and choice divergence. From the result, we confirm the SFC language reduced program memory capacity and processing time is faster than LD language.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.1
• /
• pp.107-112
• /
• 2010

When we design the control system used Programmable Logic controller(PLC), if we program a Sequential Function Chart(SFC), It is easy to understand the sequential flow of control, to maintenance the controller and to describe a program. SFC language is programmed by a single sequence, a select sequence and a parallel sequence. In a select sequence, when the select step is error, the whole process is stopped. If the error step has no connection the whole process, the loss is down when we debugging the program without stopping the whole process. Therefore, this thesis shows the efficient method of remote control for select sequence and we confirmed its feasibility through actual example.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.14 no.10
• /
• pp.5134-5139
• /
• 2013

Ladder Diagram(LD) or Sequential Function Chart(SFC) is used for the design of complex modern control system with Programmable logic controller(PLC). LD is the most widely utilized among PLC standard language. But recently, SFC is used frequently. SFC is very easy to grasp the sequential flow of control logic but is difficult for describing combinational logic. When the interrupt factor is occurred, the main program is stopped. And after the interrupt program is completed, the main program is restart. Therefore the more complex the interrupt program, the main program is interrupted downtime will be that much longer. In this paper, we propose the method for interrupt implementation without the dwell time of the main program by SFC language and confirm his feasibility through the simulation.

• Proceedings of the KSR Conference
• /
• 2008.06a
• /
• pp.1897-1902
• /
• 2008

The computer system is used in many application domains and any system error in these domains may either cause critical loss or threaten environment or human life. Though examples of these domains can be found in many areas, the system, which is used in domains for carrying passengers including rolling stocks in particular, is expected to show satisfactory operation all the time. The relay control logic, which is used in rolling stocks, is complex in hardware and occupies considerably large volume. Nevertheless, it has been used for a long time, to let the system safely operate even in the occurrence of an error in the computer system. However, the relay control logic circuit is so complex that the analysis of proper circuit operation and interlocking tends to be dependent only on the designer's experiences instead of being systematically performed. Especially, the analysis following a change, addition and deletion of a previous circuit according to the requirements from a source of demand is significantly limited. In this paper, the accuracy of relay control logic is verified by the use of properties of Petri Net model. In addition, how main circuit breaker (MCB) control circuit is modeled and analyzed by the design methodology is shown.