• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2019년도 춘계학술대회
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• pp.475-476
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• 2019

L형 터널링 전계 효과 트랜지스터 (LTFET)는 종래의 터널링 전계 효과 트랜지스터 (TFET)보다 우수한 소자로 고려된다. 그러나, 실험적으로 입증 된 LTFET은 트랩 상태의 존재로 인한 트랩-보조-터널링 (Trap-Assisted-Tunneling; TAT)에 기인한 열악한 임계 이하 기울기(SS) 특성을 나타내었다. 본 논문에서는 실험적으로 시연 된 LTFET의 저전압 바이어스에 TAT 메커니즘을 밴드 다이어그램과 TAT 재조합률 (GTAT)을 사용하여 조사한다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 추계학술대회
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• pp.241-242
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• 2017

Part of the channel in L-shaped tunnel field-effect transistor (LTFET) is very thin and suffers from quantum confinement effect. Role of quantum confinement effect on band-to-band-tunneling (BTBT) of LTFET was investigated using numerical simulation and band diagram analysis. It was found that quantum confinement effect significantly affects the BTBT mechanism of LTFET devices.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 춘계학술대회
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• pp.171-172
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• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.512-513
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• 2018

트랩-보조-터널링(Trap-Assisted-Tunneling; TAT)은 실제 터널링 전계 효과 트랜지스터 (TFET)의 임계 이하 기울기를 저하시키고 시뮬레이션에서 고려되어야한다. 그러나, 그 메커니즘은 라인 터널링 타입 L형 TFET(LTFET)에서는 잘 알려져 있지 않았다. 본 연구는 dynamic nonlocal Schenk 모델을 이용한 LTFET의 TAT 메커니즘을 연구한다. 이 연구에서는 터널링 이벤트를 위해서 phonon assisted and direct band가 모두 고려되었다.

• Journal of information and communication convergence engineering
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• 제19권4호
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.