• The Journal of the Acoustical Society of Korea
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• v.5 no.2
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• pp.19-28
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• 1986

DSP LSE을 이용하여 디지털 DTMF 수신기를 구현하는 방법으로는 IIR 디지털 필터, Counter 방법, DFT 방법, FFT 방법 및 PARCOR 방법등이 제안되어 왔다. 그 중에서도 IIR 디지털 필터를 이용 한 방법은 기존의 아나로그 DTME 수신기를 그대로 디지털화 한 것이기 때문에 성능이 제일 우수한 것 으로 알려져 있다. 그러나 IIR 디지털 필터를 이용하여 그것을 구현할 때 필터의 계수, roundoff 잡음, overflow 등 고려해야 할 사항이 많다. 본 논문에서는 이러한 문제점들을 해결하면서 CCITT 사양들을 만족하는 디지털 DTMF 수신기 구현에 관한 연구결과를 제시하였다. DSP LSI을 이용해서 수신기를 hardware 제작할 때 이 결과들을 수정없이 이용할 수 있다고 기대된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.984-990
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• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• 대한생식의학회:학술대회논문집
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• 2006.06a
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• pp.161.2-161.2
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• 2006

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.2
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• pp.34-39
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• 1976

The purpose of this thesis is to make clear the problems which would arisc from the process of making the Minicomputer by the employment of LSI, and to examine a solution to the problems. This Simulation 19 do for value performance of NOVA Emulator which designed before this. As a result of this studies, The problem of the hardware design by Microprocessor, the problem to be accompanied with application of LSI to the computer in the furture, etc. are mentioned definitely.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.26-33
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• 1984

This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.

• IE interfaces
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• v.16 no.3
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• pp.344-351
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• 2003

Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.13-16
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• 1984

This paper proposes a new layout algorithm in order to minimize chip area in one dimensional MOS - LSI composed of basic cells, such as NAND or NOR gates. The virtval gates are constructed, which represent I/O of signal lines at the left-most and at the right-most side of the MCS gate array. With this, a heuristic algorithm is realized that can minimize the number of straight connectors passing through each gate, and as the result, minimize the horizontal tracks necessary to route. The usefulness of the algorithm proposed is shown by the execution of the experimental program on practical logic circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.84-89
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• 1984

In the design of digital system, designers use multi-layer LSI to connect all signal sets between circuit modules. This paper suggests how to minimize upper street congestions and lower congestions in the single-row routing, a routing method of multi-layer LSI. This paper suggests the heuristic algorithm which minimize upper street congestions and lower street congestions by suggesting interval graph and relational operator and finding out of the order of signal sets The algorithm was implemented on a VAX-11/780 computer and illustrated by means of examples.

• The Journal of Korean Association of Computer Education
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• v.6 no.1
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• pp.1-8
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• 2003

We introduce a efficient vertical mining algorithm that reduces searching complexity for frequent k-itemsets significantly. This method includes sorting items by their LSI(Least Support Itemsets) similarity and then searching frequent itemsets in tree-based manner. The search tree structure provides several useful heuristics and therefore, reduces search space significantly at early stages. Experimental results on various data sets shows that the proposed algorithm improves searching performance compared to other algorithms, especially for a database having long pattern.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.330-335
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• 2002

The most critical issue in information retrieval system is to have adequate results corresponding to user requests. When all documents related with user inquiry retrieve, it is not easy not only to find correct document what user wants but is limited. Therefore, clustering method that grouped by corresponding documents has widely used so far. In this paper, we cluster on the basis of the meaning rather than the index term in the existing document and a LSI method is applied by this reason. Furthermore, we distinguish and analyze differences from the clustering using widely-used K-Means algorithm for the document clustering.