• Title/Summary/Keyword: LSI

Search Result 354, Processing Time 0.026 seconds

An Effective Memory Test Algorithm for Detecting NPSFs (이웃 패턴 감응 고장을 위한 효과적인 메모리 테스트 알고리듬)

  • Suh, Il-Seok;Kang, Yong-Seok;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.39 no.11
    • /
    • pp.44-52
    • /
    • 2002
  • Since memory technology has been developed fast, test complexity and test time have been increased simultaneously. In practice, March algorithms are used widely for detecting various faults. However, March algorithms cannot detect NPSFs(Neighborhood Pattern Sensitive Faults) which must be considered for DRAMs. This paper proposes an effective algorithm for high fault coverage by modifying the conventional March algorithms.

A Nano-power Switched-capacitor Voltage Reference Using MOS Body Effect for Applications in Subthreshold LSI

  • Zhang, Hao;Huang, Meng-Shu;Zhang, Yi-Meng;Yoshihara, Tsutomu
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.14 no.1
    • /
    • pp.70-82
    • /
    • 2014
  • A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

Hardware Architecture of Automatic Exposure Algorithm for CMOS Image Sensor (CMOS Image Sensor용 자동노출 알고리즘의 하드웨어 구조)

  • Mo, Sung-Wook;Park, Hyun-Sang
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.10 no.7
    • /
    • pp.1497-1502
    • /
    • 2009
  • AE(Auto exposure) is a function to maintain the exposure value of a captured image constant, and is one of the crucial functionalities of a CIS-based mobile camera. Generally AE is implemented in software, requiring a CPU and a ROM to store the corresponding software. This approach increases the hardware size at the cost of increased flexibility. In this paper, we propose an AE algorithm featuring variable frame-rate and adaptive analog gain control, as well as a FSM-based hardware architecture for a CIS-based mobile camera.

Plasma Charge Damage on Wafer Edge Transistor in Dry Etch Process (Dry Etch 공정에 의한 Wafer Edge Plasma Damage 개선 연구)

  • Han, Won-Man;Kim, Jae-Pil;Ru, Tae-Kwan;Kim, Chung-Howan;Bae, Kyong-Sung;Roh, Yong-Han
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2007.06a
    • /
    • pp.109-110
    • /
    • 2007
  • Plasma etching process에서 magnetic field 영향에 관한 연구이다. High level dry etch process를 위해서는 high density plasma(HDP)가 요구된다. HDP를 위해서 MERIE(Magnetical enhancement reactive ion etcher) type의 설비가 사용되며 process chamber side에 4개의 magnetic coil을 사용한다. 이런 magnetic factor가 특히 wafer edge부문에 plasma charging에 의한 damage를 유발시키고 이로 인해 device Vth(Threshold voltage)가 shift 되면서 제품의 program 동작 문제의 원인이 되는 것을 발견하였다. 이번 연구에서 magnetic field와 관련된 plasma charge damage를 확인하고 damage free한 공정조건을 확보하게 되었다.

  • PDF

A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

  • Choi, Moon-Ho;Yang, Byung-Do;Kim, Nam-Soo;Kim, Yeong-Seuk;Lee, Soo-Joo;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
    • /
    • v.11 no.1
    • /
    • pp.20-23
    • /
    • 2010
  • The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

故障許容電算體系의 設計와 信賴度

  • 조정완
    • Communications of the Korean Institute of Information Scientists and Engineers
    • /
    • v.1 no.1
    • /
    • pp.42-49
    • /
    • 1983
  • 전산기의 신뢰도(reliability)라 함은 사용자가 제출한 입력에 대하여 전산 기가 제공하는 결과의 신빙성의 척도라할 수 있는데, 이것은 주어진 전산기의 부 분품 하나하나가, 그리고 프로그램의 하나하나의 instruction이 설계당시에 목적한 성능을 얼마나 잘 유지하고 있는가를 측정하는 척도라고 볼 수 있습니다. 이 신 뢰도는 전산기의 수명, 필요할 때 전산기가 가동할 확율, 또는 전산기의 성능으로 나타낼 수 있습니다. 제2세대 이전의 전산기들에서는 전자공업과 전산기 기술의 불충분한 발전으로 인하여 비용과 기계의 크기의 한정 때문에 신뢰도 향상을 위 한 대책이 거의 없었습니다. 따라서 현재 볼 수 있는 American Air Line의 SABRE(Semi Automatic Business Research Environment), Bell 전화 연구소의 ESS-I, II, III(Electronic Switching System), IBM의 FMS(Future Manufacturing System)과 같은 real-time 씨스템으로서의 응용분야의 개발은 상 당히 어려운 문제였습니다. 그러나 전자공업의 비약적인 발전에 힘입어 금세대의 범용전산기의 설계가 가능하게 되었고, 오퍼레이팅 씨스템의 발전으로 인하여 multiprogramming, time-sharing, real-time 씨스템 등의 응용분야의 개발이 활발 하게 되었습니다. 이러한 응용분야의 활발한 개발과, 대규모 집적회로 (LSI)의 개 발로 ROM(Read Only Memory)의 가격화, 그리고 microprogram의 보급 등으로 특수 목적의 time sharing operation을 위한 소형 전산기가 발전하게 되었으며 종 래의 범용 전산기 대신에 CDC의 string unit과 pipeline을 이용한 STAR 100과 일리노이 대학의 256processor와 Burrough의 B6500로 구성된 ILLIAC-IV와 같은 초대형 전산기가 등장하게 되었습니다.

Toxicometallomics of Cadmium, Manganese and Arsenic with Special Reference to the Roles of Metal Transporters

  • Himeno, Seiichiro;Sumi, Daigo;Fujishiro, Hitomi
    • Toxicological Research
    • /
    • v.35 no.4
    • /
    • pp.311-317
    • /
    • 2019
  • The transport systems for metals play crucial roles in both the physiological functions of essential metals and the toxic effects of hazardous metals in mammals and plants. In mammalian cells, Zn transporters such as ZIP8 and ZIP14 have been found to function as the transporters for Mn(II) and Cd(II), contributing to the maintenance of Mn homeostasis and metallothionein-independent transports of Cd, respectively. In rice, the Mn transporter OsNramp5 expressed in the root is used for the uptake of Cd from the soil. Japan began to cultivate OsNramp5 mutant rice, which was found to accumulate little Cd, to prevent Cd accumulation. Inorganic trivalent arsenic (As(III)) is absorbed into mammalian cells via aquaglyceroporin, a water and glycerol channel. The ortholog of aquaporin in rice, OsLsi1, was found to be an Si transporter expressed in rice root, and is responsible for the absorption of soil As(III) into the root. Since rice is a hyperaccumulator of Si, higher amounts of As(III) are incorporated into rice compared to other plants. Thus, the transporters of essential metals are also utilized to incorporate toxic metals in both mammals and plants, and understanding the mechanisms of metal transports is important for the development of mitigation strategies against food contamination.

Thermal and mechanical properties of C/SiC composites fabricated by liquid silicon infiltration with nitric acid surface-treated carbon fibers

  • Choi, Jae Hyung;Kim, Seyoung;Kim, Soo-hyun;Han, In-sub;Seong, Young-hoon;Bang, Hyung Joon
    • Journal of Ceramic Processing Research
    • /
    • v.20 no.1
    • /
    • pp.48-53
    • /
    • 2019
  • Carbon fiber reinforced SiC composites (C/SiC) have high-temperature stability and excellent thermal shock resistance, and are currently being applied in extreme environments, for example, as aerospace propulsion parts or in high-performance brake systems. However, their low thermal conductivity, compared to metallic materials, are an obstacle to energy efficiency improvements via utilization of regenerative cooling systems. In order to solve this problem, the present study investigated the bonding strength between carbon fiber and matrix material within ceramic matrix composite (CMC) materials, demonstrating the relation between the microstructure and bonding, and showing that the mechanical properties and thermal conductivity may be improved by treatment of the carbon fibers. When fiber surface was treated with a nitric acid solution, the observed segment crack areas within the subsequently generated CMC increased from 6 to 10%; moreover, it was possible to enhance the thermal conductivity from 10.5 to 14 W/m·K, via the same approach. However, fiber surface treatment tends to cause mechanical damage of the final composite material by fiber etching.

Analysis of the agricultural area conversion of paddy to field based on reservoir irrigation region (저수지 수혜구역단위 논 전작화 패턴 분석)

  • Park, Jin Seok;Jang, Seong Ju;Hong, Rok Gi;Hong, Joo Pyo;Song, In Hong
    • Proceedings of the Korea Water Resources Association Conference
    • /
    • 2021.06a
    • /
    • pp.467-467
    • /
    • 2021
  • 기존 저수지 농업용수는 주로 논의 벼재배 용수공급을 목적으로 설계되었지만, 논 지역 타작물 재배 지원 등의 정책으로 논에서 밭으로 전작화가 증가함에 따라 농업용수의 효율적 분배를 위한 논의 전작화 패턴 분석이 필요한 실정이다. 이에 본 연구에서는 공공데이터 포털의 2019년 팜맵을 활용하여 최신 경지 현황을 파악하고, 환경부의 2007년, 2019년 토지피복지도를 이용하여 전작화 패턴을 분석하였다. 구축된 팜맵과 토지피복지도는 환경부 토지피복분류 기준 농업지역 중분류로 일치시켜 분석에 활용되었다. 논, 밭, 시설재배지 등의 농경지 이용 현황 및 전작화 추이는 전국 단위, 권역 단위로 분석되었고, 주요 시도와의 공간적 거리를 전작화 영향인자로 설정하여 DUP(Degree of Urban Proximity) 등의 지표로 그 영향을 확인하였다. 또한, 전체 경지 중 논, 밭의 면적과 증감 추이를 ACR(Area Change Rate) 등의 지표로 전작화 규모를 파악하였고, LPI(Largest Patch Index), LSI(Landscape Shape Index) 등의 지표로 개별/집단화 전작의 패턴분석을 수행하였다. 본 연구로 제시된 저수지 수혜 구역별 논의 전작화 패턴은 논 벼재배와 농업용수 수요 특성이 상이한 밭작물에 안정적 용수공급 체계 구축 등의 기초자료로 활용 가능할 것으로 생각된다.

  • PDF

Resolution improvement of a CMOS vision chip for edge detection by separating photo-sensing and edge detection circuits (수광 회로와 윤곽 검출 회로의 분리를 통한 윤곽 검출용 시각칩의 해상도 향상)

  • Kong, Jae-Sung;Suh, Sung-Ho;Kim, Sang-Heon;Shin, Jang-Kyoo;Lee, Min-Ho
    • Journal of Sensor Science and Technology
    • /
    • v.15 no.2
    • /
    • pp.112-119
    • /
    • 2006
  • Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.