• Proceedings of the Korean Information Science Society Conference
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• 1998.10b
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• pp.217-219
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• 1998

시간지원 데이터베이스는 시간에 따른 이력데이터가 단조증가 형태를 띄고 있는데 반해 이력질의는 주로 최근 생성된 데이터에 관한 질의 비율이 상대적으로 높다. 또한 방대한 양의 데이터를 관리하기 위해 3차 저장장치를 효율적으로 사용할 필요가 있으며 이를 위해 시간지원 데이테베이스 관리시스템은 특정 시간마다 이력데이터를 3차 저장자치에 이동시키는 버큐밍(Vacuming)작업을 수행한다. 이 논문에서는 이력데이터 페이지와 현재 데이터 페이지의 시간선상에서의 참조 빈도수를 고려하며, 이력질의에 대하여는 페이지의 과거의 참조밀도 이력을 고려하여 버퍼를 관리하는 LRU/PRD기법을 제안한다.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.127-129
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• 2001

본 논문에서는 실시간성을 기반으로 하는 VOD시스템을 위한 우선 순위 가중치 기반의 가상 메모리 교체 기법을 제안하였다. 전통적인 운영체제에서 사용하는 가상 메모리 기법인 LRU와 LFU등은 우선 순위를 전혀 고려하지 않기 때문에 실시간 기반의 운영체제에는 전혀 적합하지 않다. 본 논문에서는 실시간성을 유지하기 위하여 프로세스의 우선 순위에 기반 한 차등화 된 가상 메모리 기법을 제안하였다. 그리고 낮은 우선 순위를 고려하여 주기억장치의 프로세스 공간 점유율도 고려하였다. 실험 결과, 서로 차등화 된 페이지 교체횟수를 보였고 일정한 수준의 우선 순위에 따라서 차등화 된 공간 점유율을 유지하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.409-411
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• 2002

본 논문에서는 스트리밍 미디어 캐슁 서버의 효율적인 캐슁 구조를 위하여 참조 횟수, 참조량, 참조 시간 둥의 정량적인 인자들과 사용자 요구 주기를 적용하여 최근 참조 경향에 높은 가중치를 부여함으로써 변화하는 콘텐츠 선호 경향에 빠르게 적응하는 가중치 기반의 캐쉬 교체 정책을 제안한다. 성능 분석은 시뮬레이션 환경 구축을 통해 실험하였으며 LRU, LFU와 SEG 캐쉬 정책과 비교 분석하여 향상된 결과를 보였다.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.173-180
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• 2006

An airborne radar is an essential aviation electronic system of the aircraft to perform various missions in all weather environments. This paper presents the design, development, and test results of the multi-mode pulsed Doppler radar system test model for helicopter-borne flight test. This radar system consists of 4 LRU units, which include ANTU(Antenna Unit), TRU(Tx Rx Unit), RSDU(Radar Signal & Data Processing Unit) and DISU(Display Unit). The developed technologies include the TACCAR processor, planar array antenna, TWTA transmitter, coherent I/Q detector, digital pulse compression, DSP based Doppler FFT filtering, adaptive CFAR, IMU, and tracking capability. The design performance of the developed radar system is verified through various helicopter-borne field tests including MTD (Moving Target Detector) capability for the Doppler compensation due to the moving platform motion.

• Journal of the Korea Society of Computer and Information
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• v.10 no.6 s.38
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• pp.153-166
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• 2005

Existing single cache structure has shown difference of hit-ratio according to individually replacement strategy However. It needs new improved cache structure for reducing network traffic and providing advanced hit-ratio. Therefore, this Paper design push agent model using dual cache for increasing hit-ratio by reducing server overload and network traffic by repetition request of persistent and identical information. In this model proposes dual cache structure to do achievement replace gradual cache using by two caches storage space for reducing server overload and network traffic. Also, we show new cache replace techniques and algorithms which executes data update and delete based on replace strategy of Log(Size) +LRU, LFU and PLC for effectiveness of data search in cache. And through an experiment, it evaluates Performance of dual cache push agent model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1229-1240
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• 1998

In this paper, we provide a design of DAVIC VOD service system with proxy servers which perform caching of video streams. Proxy servers are placed between a service provider system and service consumer systems. They provide video services to consumers on behalf of the service provider, therefore they reduce the loads of service providers and network. The operation of a proxy server depends on whether the requested program is in its storage. If this is the case, the prosy servere takes all the controls, but if the proxy does not have the program, it forwards the service request the proxy server takes all the controls, but if the prosy does not have the program, it forwards the service request to a service provider. While the service provider system provides the program to the consumer, the proxy copies and caches the program. The proxy server executes cache replacement, if necessary. We show by simultion that the LFU is the most efficiency caching replacement algorithm among the typical algorithms such as LRU, LFU, FIFO.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.913-917
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• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of Korea Game Society
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• v.3 no.1
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• pp.67-73
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• 2003

Most web caches save documents temporarily into themselves on the basis of those documents. And when a corresponding document exists within the cache on wei s request, web cache sends the document to corresponding user. On the contrary, when there is not any document within the cache, web cache requests a new document to the related server to copy the document into the cache and then rum it back to user. Here, web cache uses a replacement policy to change existing document into a new one due to exceeded capacity of cache. Typical replacement policy includes document-based LRU or LFU technique and other various replacement policies are used to replace the documents within cache effectively. However, these replacement policies function only with regard to the time and frequency of document request, not considering the popularity of each web site. Based on replacement policies with regard to documents on frequent requests and the popularity of each web site, this paper aims to present the document replacement policies with regard to the popularity of each web site, which are suitable for latest network environments to enhance the hit-ratio of cache and efficiently manage the contents of cache by effectively replacing documents on intermittent requests by new ones.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.