• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• Journal of Astronomy and Space Sciences
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• v.33 no.3
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• pp.229-236
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• 2016

We present proton-induced single event effects (SEEs) and γ-ray-induced total ionizing dose (TID) data for 1 Gbit lowpower double data rate synchronous dynamic random access memory (LPDDR SDRAM) fabricated on a 5 μm epitaxial layer (54 nm complementary metal-oxide-semiconductor (CMOS) technology). We compare our radiation tolerance data for LPDDR SDRAM with those of general DDR SDRAM. The data confirms that our devices under test (DUTs) are potential candidates for space flight applications.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• The Journal of Korean Institute of Next Generation Computing
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• v.13 no.4
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• pp.40-51
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• 2017

Recently, as mobile workloads are becoming more data-intensive, high data bandwidth is required for mobile memory which also consumes non-negligible system energy. A variety of researches and technologies are under development to improve and optimize mobile memory technologies. However, a comprehensive study on the latest mobile memory technologies (LPDDR or Wide I/O) has not been extensively performed yet. To construct high-performance and energy-efficient mobile memory systems, quantitative and detailed analysis of these technologies is crucial. In this paper, we simulate the computer system which adopts mobile DRAM technologies (Wide I/O and LPDDR3). Based on our detailed and comprehensive results, we analyze important factors that affect performance and energy-efficiency of mobile DRAM technologies and show which part can be improved to construct better systems.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06d
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• pp.24-27
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• 2011

최근 스마트 폰 등 모바일 기기의 폭발적인 성장에 의해 내장 프로세서인 ARM 프로세서 기반 기기들이 활발히 개발되어 사용되고 있다. 이에 따라 상대적으로 저성능, 저 전력화에 치중하였던 내장 프로세서도 고성능화를 위한 고속 동작 및 멀티코어 프로세서를 개발하여 사용하게 되었으며, 메모리 동작 속도 역시 빠르게 발전하고 있다. 특히 모바일 기기 등에 사용 되는 저전력 메모리인 LPDDR2 소자 등의 개발에 따라 빠른 동작 속도를 가지도록 개발되고 있다. 그러나 시스템 온 칩(SoC, System on Chip) 형태로 제작되는 ARM 프로세서 기반의 SoC는 다양한 하드웨어 가속기 등을 함께 내장하고 있고, 저 전력화를 위한 버스 구조 등에 의하여 온 칩 버스의 속도 향상이 고성능 범용 시스템에 비하여 낮은 수준이다. 본 연구에서는 이러한 점을 고려하여, 프로세서 코어와 메모리 소자의 동작 속도 향상에 의하여 얻을 수 있는 성능 향상과, 상대적으로 낮은 버스 동작 속도에 의하여 저하되는 성능의 정도를 분석하고 이를 극복하기 위한 방안을 검토하였다.