• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.55-68
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• 2001

This paper presents a new ALU architecture to minimize glitching power consumption which is appeared in the conventional one with P(carry propagation)/G(carry generation) blocks. In general, A lot of glitches generated once are propagating into the next stage of circuits to make unnecessary power dissipation. Therefore, a new ALU architecture which removes the glitches at the output of P/G blocks is presented in this paper. If a lot of glitches at the output of P/G blocks are removed, then the signal transitions caused by glitches are reduced in the sum generation block and hence power consumption is also reduced. A latch is inserted into the conventional P/G blocks to remove the glitches at the output of P/G blocks. Latch enable signal can make a role in eliminating a lot of glitches at the P/G's outputs by controlling output enable time. Experimental results from HSPICE simulations with implementing 16-b ALU show 28% reduction in glitching power consumption with negligible delay penalty.

• Journal of IKEEE
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• v.21 no.1
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• pp.7-12
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• 2017

This paper proposed the ESD protection circuit for the high-voltage applications with latch-up immunity and high area efficiency. The proposed circuit has high holding voltage compared to the conventional SCR by inserting the floating regions and applying the segmentation layout. It has the area efficiency is more higher due to the segmentation layout. The proposed circuit has the higher holding voltage of the 21.67V than the 3.39V of the conventional SCR. The electrical characteristics of the proposed circuit was investigated by TCAD simulator, and was proved through the fabrication by using the 0.18 BCD process.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.2
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• pp.56-67
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• 2006

The reliability and failure mode effect analysis are effective means to achieve efficient and cost-reduction design for satellite development. The failure rate of COTS (Commercial-Off-The-Shelf) parts required for reliability analysis is not usually provided from the manufacturer. Space environment factors based on empirical data obtained from MIL-HDBK-217F can be applicable to the reliability calculation. As a radiation environment factor, the occurrence rate of SEL (Single Event Latch-up) is additionally incorporated for the failure rate prediction. In this paper, the statistical reliability analysis method for low-cost small satellite using COTS parts is suggested. This statistical reliability analysis was applied to HAUSAT-2 small satellite whose electronic boxes are consisted of many COTS parts to calculate the system reliability at the end of design mission life.

• Journal of IKEEE
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• v.24 no.4
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• pp.1156-1161
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• 2020

In this paper, we propose a new ESD protection circuit with improved electrical characteristics through structural changes of the existing one-way SCR. The proposed ESD protection circuit has high holding voltage characteristics due to the inserted N+ floating and P+ floating regions, and thus the latch-up immunity characteristics are improved. In addition, structural change enables ESD discharge in four types of Zapping mode (PD, PS, ND, NS), and has superior area efficiency than unidirectional SCR. In addition, the P+ floating and N+ floating lengths corresponding to the base length of the parasitic bipolar transistor, and the distance between P+ floating and N+ floating were designated as design variables, and the high holding voltage was verified through Synopsys' TCAD Simulator.

• Journal of Software Assessment and Valuation
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• v.16 no.2
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• pp.109-115
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• 2020

In this paper, the problem that occurs when negative voltage is generated using an inexpensive buck device in an IT device that is supplied with a single power by an adapter or battery is analyzed. For the cause analysis, the principle of operation of the buck device and the principle of the inverter circuit were examined, and the circuit characteristics of the inverter circuit were analyzed using the buck device. As a result of the analysis, it was confirmed that the inverter circuit using the buck device initially needs a large starting current, and in particular, in the case of a current capacity that is less than the starting current in the circuit that supplies power, it was confirmed that it could fall into a state similar to the latch-up phenomenon. In order to confirm the analysis result, an experimental circuit was constructed and the input current was checked. If the supply current is sufficient, it is confirmed that over-current flows and starts. If the supply current is insufficient, the circuit cannot start and a latch-up phenomenon occurs.

• Design & Manufacturing
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• v.17 no.3
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• pp.15-20
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• 2023

In the fine blanking process, which is a press operation known for producing parts with narrow clearances and high precision through the application of high pressure, die roll often occurs during the shearing process when the punch penetrates the material. This die roll phenomenon can significantly reduce the functional surface of the parts, leading to decreased product performance, strength, and fatigue life. In this research, we conducted an in-depth analysis of the factors influencing die roll in the curvature area of the fine blanking process and identified its root causes. Subsequently, we designed and experimentally verified a die roll reduction process specifically tailored for the door latch manufacturing process. Our findings indicate that die roll tends to increase as the curvature radius decreases, primarily due to the heightened bending moment resulting from reduced shape width-length. Additionally, die roll is triggered by the absorption of initial punch energy by scrap material during the early shearing phase, resulting in lower speed compared to the product area. To mitigate the occurrence of die roll, we strategically selected the Shaving process and carefully determined the shaving direction and clearance area length. Our experiments demonstrated a promising trend of up to 75% reduction in die roll when applying the Shaving process in the opposite direction of pre-cutting, with the minimum die roll observed at a clearance area length of 0.2 mm. Furthermore, we successfully implemented this approach in the production of door latch products, confirming a significant reduction in die roll. This research contributes valuable insights and practical solutions for addressing die roll issues in fine blanking processes.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1953-1955
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• 1999

The effects of the local lifetime control on the characteristics of IGBT are investigated using the 2-dimensional device simulator, MEDICI. Many lumped resistive turn-off simulations are carried out to analyze the effects of the minority carrier lifetime, the width, and the position of the region with a reduced local minority carrier lifetime. As a result of these simulations, it is concluded that the on state voltage drop$(V_{CE,SAT})$ is only slightly increased while the switching behavior is greatly improved if the low lifetime region is properly set. And these results are compared with IGBTs having uniform lifetime.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• The Transactions of the Korea Information Processing Society
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• v.1 no.2
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• pp.272-278
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• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.588-591
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• 2012

인터넷 사용량의 증가와 네트워크 망 기술의 발달로 인해 데이터는 대용량화 되어지는 반면 휴대기기는 고속화와 소형화가 되어 지면서 직렬 포트를 이용한 외부 장치들과 데이터 송 수신이 가능한 인터페이스가 요구되고 있다. 본 논문에서는 16바이트의 버퍼링을 제공하는 UART 인터페이스를 HDL로 설계하여 내부 모듈과 외부 장치들 간의 데이터 전송이 가능하도록 하였고, Modelsim 6.1로 시뮬레이션 하였다.