• Title/Summary/Keyword: Korean mask

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PM OLED Fabrication with New Method of Metal Cathode Deposition Using Shadow Mask

  • Lee, Ho-Chul;Kang, Seong-Jong;Yi, Jung-Yoon;Kim, Ho-Eoun;Kwon, Oh-June;Hwang, Jo-Il;Kim, Jeong-Moon;Roh, Byeong-Gyu;Kim, Woo-Young
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.987-989
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    • 2006
  • 1.52" $130(RGB){\times}130$ full color PM OLED device with $70\;{\mu}m{\times}210\;{\mu}m$ of sub-pixel pitch was fabricated using shadow mask method for metal cathode deposition. Instead of conventional patterning process to form cathode separator via photolithography, regularly patterned shadow mask was applied to deposit metal cathode in this OLED display. Metal cathode was patterned via 2-step evaporation using shadow mask with shape of rectangular stripe and its alignment margin is $2.5\;{\mu}m$. Technical advantages of this method include reduction of process time according to skipping over photolithographic process for cathode separator and minimizing pixel shrinkage caused by PR cathode separator as well as improving lifetime of OLED device.

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Simulation and Mask Drawing of Single Flux Quantum AND gate (단자속 양자 AND gate의 시뮬레이션과 Mask Drawing)

  • 정구락;임해용;박종혁;강준희;한택상
    • Progress in Superconductivity and Cryogenics
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    • v.4 no.1
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    • pp.35-39
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    • 2002
  • We have simulated and laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. SFQ AND gate circuit is a combination of two D Flip-Flop. D Flip-Flop and dc SQUID are the similar shape form the fact that it has the loop inductor and two Josephson junction We obtained perating margins and accomplished layout of the AND gate. We got the margin of $\pm$38%. over. After layout, we drew mask for fabrication of SFQ AND sate. This mask was included AND gate, dcsfq, sfqdc, rs flip-flop and jtl.

An Edge Detection Algorithm using Modified Mask in AWGN Environment (AWGN 환경에서 변형된 마스크를 이용한 에지 검출 알고리즘)

  • Lee, Chang-Young;Kim, Nam-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.05a
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    • pp.892-894
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    • 2013
  • Edge has been utilized in various application fields with development of technique of digital image processing. In conventional edge detection methods, there are some methods using mask including Sobel, Prewitt, Roberts and Laplacian operator. Those methods are that implement is simple but generates errors of edge detection in images added AWGN(additive white Gaussian noise). Therefore, to compensate the defect of those methods, in this paper, an edge detection algorithm using modified mask is proposed, and it showed superior edge detection property in AWGN.

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Nanoscale Fabrication in Aqueous Solution using Tribo-Nanolithography

  • Park, Jeong-Woo;Lee, Deug-Woo;Kawasegi, Noritaka;Morita, Noboru
    • International Journal of Precision Engineering and Manufacturing
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    • v.7 no.4
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    • pp.8-13
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    • 2006
  • Nanoscale fabrication of silicon substrate in an aqueous solution based on the use of atomic force microscopy was demonstrated. A specially designed cantilever with a diamond tip, allowing the formation of a mask layer on the silicon substrate by a simple scratching process (Tribo-Nanolithography, TNL), has been applied instead of the conventional silicon cantilever for scanning. A slant nanostructure can be fabricated by a process in which a thin mask layer rapidly forms on the substrate at the diamond tip-sample junction along scanning path of the tip, and simultaneously, the area uncovered with the mask layer is etched. This study demonstrates how the TNL parameters can affect the formation of the mask layer and the shape of 3-D structure, hence introducing a new process of AFM-based nanolithography in aqueous solution.

DPSS UV Laser Projection Ablation of IC Substrates using an INVAR Mask (INVAR 마스크 응용 반도체 기판 소재의 고체 UV 레이저 프로젝션 어블레이션)

  • Sohn, Hyonkee;Choe, Hanseop;Park, Jong-Sig
    • Laser Solutions
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    • v.15 no.4
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    • pp.16-19
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    • 2012
  • Due to the fact that the dimensions of circuit lines of IC substrates have been forecast to reduce rapidly, engraving the circuit line patterns with laser has emerged as a promising alternative. To engrave circuit line patterns in an IC substrate, we used a projection ablation technique in which a metal (INVAR) mask and a DPSS UV laser instead of an excimer laser are used. Results showed that the circuit line patterns engraved in the IC substrate have a width of about 15um and a depth of $13{\mu}m$. This indicates that the projection ablation with a metal mask and a DPSS UV laser could feasibly replace the semi-additive process (SAP).

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A Study on Fashion Design Using Masks (가면(假面)(Mask)을 활용(活用)한 의상(衣裳)디자인 연구(硏究))

  • Im, Hyung-Ran;Lee, Mi-Sook
    • Journal of Fashion Business
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    • v.8 no.2
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    • pp.154-167
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    • 2004
  • The purpose of this study was to develop fashion designs using masks on the basis of plasticity of masks. This study was conducted both theoretically and empirically. In a theoretical study, mask-related research and fashion-related literature were examined. In an empirical study, masks used in collections since the 1990's were analyzed through fashion magazines and fashion web sites. Based on such theoretical researches, masks used in modern fashion collections were divided into accessories and clothing to analyze and three fashion designs were developed on the basis of results described above. This study intended to express a romantic look with primitive mood that added formative elements of a mask to the design concept of "Romantic-Primitive". First, forms of masks were simplified and deconstructed and then some methods such as textile printing, leather handicraft, or applique were expressed.

Semiconductor Process Inspection Using Mask R-CNN (Mask R-CNN을 활용한 반도체 공정 검사)

  • Han, Jung Hee;Hong, Sung Soo
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.3
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    • pp.12-18
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    • 2020
  • In semiconductor manufacturing, defect detection is critical to maintain high yield. Currently, computer vision systems used in semiconductor photo lithography still have adopt to digital image processing algorithm, which often occur inspection faults due to sensitivity to external environment. Thus, we intend to handle this problem by means of using Mask R-CNN instead of digital image processing algorithm. Additionally, Mask R-CNN can be trained with image dataset pre-processed by means of the specific designed digital image filter to extract the enhanced feature map of Convolutional Neural Network (CNN). Our approach converged advantage of digital image processing and instance segmentation with deep learning yields more efficient semiconductor photo lithography inspection system than conventional system.

The Analysis of Three-dimensional Oxidation Process with Elasto-viscoplastic Model

  • Lee Jun-Ha;Lee Hoong-Joo
    • Transactions on Electrical and Electronic Materials
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    • v.5 no.6
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    • pp.215-218
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    • 2004
  • This paper presents a three-dimensional numerical simulation for thermal oxidation process. A new elasto-viscoplastic model for robust numerical oxidation simulation is proposed. The three-dimensional effects of oxidation process such as mask lifting effect and corner effects are analyzed. In nano-scale process, the oxidant diffusion is punched through to the other side of the mask. The mask is lifted so the thickness of oxide region is greatly enhanced. The compressive pressure during the oxidation is largest in the mask corner of the island structure. This is because the masked area near the corner is surrounded by an area larger than the others in the island structure. This stress induces the retardation of the oxide growth, especially at the masked corner in the island structure.

n-type porous silicon formation using Pt mask & its application (Pt를 mask로 이용한 n-type 다공질 실리콘 형성과 응용)

  • Kang, Chul-Goo;Min, Nam-Ki;Lee, Seung-Jae
    • Proceedings of the KIEE Conference
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    • 2000.07c
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    • pp.1760-1762
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    • 2000
  • 본 논문은 기존의 $Si_{3}N_4$, SiN 물질 대신 Pt를 사용해 HF 용액속에서 다공질 실리콘과 전극을 동시에 형성하는 기술을 개발하였다. Pt를 실리콘 웨이퍼 위에 직접 증착한 후 습식 에칭과 Lift-off 공정을 사용하여 Pt를 패터닝하였다. 습식 에칭은 에칭용액의 온도를 일정하게 유지하는 것이 중요하며, 증착한 Pt 박막이 BOE 에칭에 견디고, Lift-off 공정이 가능하기 위해서는 기판온도를 l100$^{\circ}C$ 이하로 해야한다. Pt를 사용하면 기존의 mask에서 발생하는 가장자리 부분에서의 전류 집중이 방지되기 때문에 다공질 실리콘이 일정한 깊이로 형성되고, Al대신 오믹 전극으로 사용할 수 있다. 현재 Pt를 mask와 전극으로 이용한 P-I-N UV detector, 광 바이오센서, 습도센서 제작등에 응용 연구가 진행되고 있다.

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Optimization of the Power MOSFET with Fixed Device Dimensions (고정된 소자치수를 갖는 전력 MOSFET의 최적화)

  • Choi, Yearn-Ik;Hwang, Kue-Han;Park, Il-Yong
    • Proceedings of the KIEE Conference
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    • 1996.11a
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    • pp.457-461
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    • 1996
  • An optimum design methodology for the power MOSFET's with a predetermined mask is proposed and verified by comparing with the results of MEDICI simulation and the data of commercially available devices. Optimization is completed by determining a doping concentration and a thickness of the epitaxial layer which satisfy a specific voltage and current rating requirements as well as a minimum on-resistance for the mask set. The commercial HEX-1 mask set with a die area of $40.4{\times}10^{-3}\;cm^2$ and a T0-220 package has the on-resistance of $1.5{\Omega}$ at 200 V/2.5 A rating while the M-1 mask from this study exhibits $0.6{\Omega}$ on-resistance at 200 V/6 A. The 60 % reduction in the on-resistance and 58 % enhancement in the current rating have been obtained by the proposed method.

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