• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.4
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• pp.45-52
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• 2008

The slide resynchronization attack on Grain-v1 was proposed in [5]. Given the keystream sequence, this attack can generate the 1-bit shifted keystream sequence generated by Grain-v1. In this paper, extending the attack proposed in [5], we propose the key recovery attack on Grain-v1 using the related-key. Using the weakness of the initialization procedure of Grain-v1, this attack recover the master key with $2^{25.02}$ Ⅳs and $2^{56}$ time complexity. This attack is the first known key recovery attack on Grain-v1.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.1
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• pp.139-146
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• 2003

In this paper we demonstrate a cryptanalysis of the stream cipher LILI-128. Our approach to analysis on LILI-128 is to solve an overdefined system of multivariate equations. The LILI-128 keystream generato $r^{[8]}$ is a LFSR-based synchronous stream cipher with 128 bit key. This cipher consists of two parts, “CLOCK CONTROL”, pan and “DATA GENERATION”, part. We focus on the “DATA GENERATION”part. This part uses the function $f_d$. that satisfies the third order of correlation immunity, high nonlinearity and balancedness. But, this function does not have highly nonlinear order(i.e. high degree in its algebraic normal form). We use this property of the function $f_d$. We reduced the problem of recovering the secret key of LILI-128 to the problem of solving a largely overdefined system of multivariate equations of degree K=6. In our best version of the XL-based cryptanalysis we have the parameter D=7. Our fastest cryptanalysis of LILI-128 requires $2^{110.7}$ CPU clocks. This complexity can be achieved using only $2^{26.3}$ keystream bits.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.2
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• pp.25-32
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• 2006

In this paper, we propose a fast correlation attack on the shrinking and self-shrinking generator. This attack is an improved algorithm or the fast correlation attack by Zhang et al. at CT-RSA 2005. For the shrinking generator, we recover the initial state of generating LFSR whose length is 61 with $2^{15.43}$ keystream bits, the computational complexity of $2^{56.3314}$ and success probability 99.9%. We also recover the initial state of generating LFSR whose length is $2^{40}$ of the self-shrinking generator with $2^{45.89}$ keystream bits, the computational complexity of $2^{112.424}$ and success probability 99.9%.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.12-15
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• 2001

A summation generator creates sequence from addition with carry of LFSR (Linear Feedback Shift Register) sequences. Similarly, it is possible to generate keystream by bitwise exclusive-oring on two FCSR sequences. In this paper, we described the cryptographic properties of a sequence generated by the FCSRs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2507-2513
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• 2010

In this paper, we show that the shrinking generator with two LFSR whose characteristic polynomials are primitive is an interleaving generator and analyze phase shifts in shrunken sequence. Also for a given intercepted sequence of shrunken sequence, we propose. the method of reconstructing some deterministic bits of the shrunken sequence using phase shifts.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1075-1078
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• 2002

스트림 암호 시스템에서는 비선형 결합 LFSR 키 수열을 이용하였다. 주기가 존재하고 상관관계 공격에 약한 비선형 LFSR 키 수열의 문제를 개선하기 위해 제안된 카오스 키 수열은 균형성과 랜덤특성을 만족하지 못하고 있다. 따라서, 본 연구에서는 적응적 임계값 적용 방법을 이용하여 균형성과 랜덤특성을 만족하는 카오스 키 수열 생성 기법을 제안하였다. 본 연구에서 제안한 키 수열 생성 기법은 로지스틱 방정식을 이용하여 키 수열 생성을 위한 카오스 신호를 만든 다음 카오스 신호를 적응적 임계값 적용방법을 통해 '0'과 '1'로 양자화하여 키 수열을 생성한다. 제안한 알고리즘으로 생성된 키 수열의 특징을 분석한 결과 균형성과 랜덤특성이 기존의 카오스 키 수열에 비해 개선되었음을 알 수 있다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• Journal of information and communication convergence engineering
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• v.8 no.2
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• pp.129-135
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• 2010

Wireless sensor networks (WSNs) are an emerging technology and offers economically viable monitoring solution to many challenging applications. However, deploying new technology in hostile environment, without considering security in mind has often proved to be unreasonably unsecured. Apparently, security techniques face many critical challenges in WSNs like data security and secrecy due to its hostile deployment nature. In order to resolve security in WSNs, we propose a novel and efficient secure framework called TriSec: a secure data framework for wireless sensor networks to attain high level of security. TriSec provides data confidentiality, authentication and data integrity to sensor networks. TriSec supports node-to-node encryption using PingPong-128 stream cipher based-privacy. A new PingPong-MAC (PP-MAC) is incorporated with PingPong stream cipher to make TriSec framework more secure. PingPong-128 is fast keystream generation and it is very suitable for sensor network environment. We have implemented the proposed scheme on wireless sensor platform and our result shows their feasibility.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.9
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• pp.885-892
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• 2016

The nonlinear sequence generator called the shrinking generator was designed as nonlinear keystream generator composed by two maximum-length LFSRs. The shrunken sequences generated by the shrinking generator are included in the class of interleaved sequences and can be modelled as one of the output sequences of cellular automata (CA). In this paper, we propose a method for synthesizing a 90/150 CA-based sequence generator to generate a family of sequences with the same characteristic polynomial as the shrunken sequences.