• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.1
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• pp.47-57
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• 2003

In this paper, we firstly evaluate the resistance of the reduced 5-round version of the block cipher CIKS-1 against linear cryptanalysis(LC) and show that we can attack full-round CIKS-1 with \ulcorner56-bit key through the canonical extension of our attack. A feature of the CIKS-1 is the use of both Data-Dependent permutations(DDP) and internal key scheduling which consist in data dependent transformation of the round subkeys. Taking into accout the structure of CIKS-1 we investigate linear approximation. That is, we consider 16 linear approximations with p=3/4 for 16 parallel modulo $2^2$ additions to construct one-round linear approximation and derive one-round linear approximation with the probability P=1/2+$2^{-17}$ by Piling-up lemma. Then we present 3-round linear approximation with 1/2+$2^{-17}$ using this one-round approximation and attack the reduced 5-round CIKS-1 with 64-bit block by LC. In conclusion we present that our attack requires $2^{38}$chosen plaintexts with a probability of success of 99.9% and about $2^{67-7}$encryption times to recover the last round key.(But, for the full-round CIKS-1, our attack requires about $2^{166}$encryption times)

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.6
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• pp.1295-1305
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• 2017

There is SEED cryptosystem in domestic block cipher standard. This code was drafted by the Korea Information Security Agency (KISA) in October 1998 and underwent a public verification process in December of the same year, which resulted in the final amendment to improve safety and performance. Unlike DES, it is a 128-bit block cipher that has been passed through various processes and established in 2005 as an international standard. It is a block cipher with a pastel structure like DES, but the input bit block has been increased to 128 bits, double DES. In this paper, first, we introduce the general algorithm of SEED cryptosystem and analyzed mathematically generating principle of key-value which is used in F-function. Secondly, we developed a table that calculates the exponent of the primitive element ${\alpha}$ corresponding to the 8-bit input value of the S-function and finally analyzed calculating principle of S-function designed in G-function through the new theorem and example. Through this course, we hope that it is to be suggest the ideas and background theory needed in developing new cryptosystem to cover the weakness of SEED cryptosystem.

• Journal of KIISE:Software and Applications
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• v.31 no.2
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• pp.126-136
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• 2004

This paper proposes a new content-based image retrieval algorithm using color-spatial information. For the purpose, the paper suggests two kinds of indexing key to prune away irrelevant images to a given query image; MCS(Main Colors' Set), which is related with color information and DBS (Distribution Block Signature), which is related with spatial information. After successively applying these filters to a database, we could get a small amount of high potential candidates that are somewhat similar to the query image. Then we would make use of new QM(Quad modeling) and relevance feedback mechanism to obtain more accurate retrieval. It would enhance the retrieval effectiveness by dynamically modulating the weights of color-spatial information. Experiments show that the proposed algorithm can apply successfully image retrieval applications.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.499-502
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• 2001

Fractal image coding suffers from the long search time of domain pool although it provides many properties including the high compression ratio. We find that the normalized variance of a block is independent of contrast, brightness. Using this observation, we introduce a self similar block searching method employing the d-dimensional nearest neighbor searching. This method takes Ο(log/N) time for searching the self similar domain blocks for each range block where N is the number of domain blocks. PSNR (Peak Signal Noise Ratio) of this method is similar to that of the full search method that requires Ο(N) time for each range block. Moreover, the image quality of this method is independent of the number of edges in the image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.6
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• pp.1361-1369
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• 1996

Motion estimation is one of the key components for high quality video coding. In this paper, a new motion estimation scheme for MPEG-like video coder is suggested. The proposed temporally adaptive motion estimation scheme consists of five functional blocks: Temporal subband analysis (TSBA), extraction of temporal information, scene change detection (SCD), picture type replacement (PTR), and temporally adapted block matching algorithm (TABMA). Here all the functional components are based on the temporal subband analysis. In this papre, we applied the analysis part of subband decompostion to the temporal axis of moving picture sequence, newly defined the temporal activity distribution (TAD) and average TAD, and proposed the temporally adapted block matching algorithm, the scene change detection algorithm and picture type replacement algorithm which employed the results of the temporal subband analysis. A new block matching algorithm TABMA is capable of controlling the block matching area. According to the temporal activity distribution of objects, it allocates the search areas nonuniformly. The proposed SCD and PTR can prevent unavailable motion prediction for abrupt scene changes. Computer simulation results show that the proposed motion estimation scheme improve the quality of reconstructed sequence and reduces the number of block matching trials to 40% of the numbers of trials in conventional methods. The TSBA based scene change detection algorithm can detect the abruptly changed scenes in the intentionally combined sequence of this experiment without additional computations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Journal of Multimedia Information System
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• v.4 no.4
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• pp.205-210
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• 2017

This paper presents a verification watermarking applied to healthcare information management. The proposed method uses the whole region based on the public-key cryptograph, which is transformed by the DWT transform to integrity verification. Furthermore, the public-key cryptograph algorithm is used for the embedded watermark image. We adaptively select the upper bit-plane including the LSB parts of each block when the watermark is inserted.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.29 no.2
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• pp.123-130
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• 2016

With the development of fast construction mode in shipbuilding market, the demand on accuracy management of hull is becoming higher and higher in shipbuilding industry. In order to enhance production efficiency and reduce manufacturing cycle time in shipbuilding industry, it is important for shipyards to have the accuracy of ship components evaluated efficiently during the whole manufacturing cycle time. In accurate shipbuilding process, block accuracy is the key part, which has significant meaning in shortening the period of shipbuilding process, decreasing cost and improving the quality of ship. The key of block accuracy control is to create a integrate block accuracy controlling system, which makes great sense in implementing comprehensive accuracy controlling, increasing block accuracy, standardization of proceeding of accuracy controlling, realizing "zero-defect transferring" and advancing non-allowance shipbuilding. Generally, managers of accuracy control measure the vital points at section surface of block by using the heavy total station, which is inconvenient and time-consuming for measurement of vital points. In this paper, a new measurement method based on point clouds technique has been proposed. This method is to measure the 3D coordinates values of vital points at section surface of block by using 3D scanner, and then compare the measured point with design point based on ICP algorithm which has an allowable error check process that makes sure that whether or not the error between design point and measured point is within the margin of error.