• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.3
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• pp.105-108
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• 2015

In this paper, we propose a differential fault analysis on symmetric SPN block cipher with bitslice involution S-box in 2011. The target block cipher was designed using AES block cipher and has advantage about restricted hardware and software environment using the same structure in encryption and decryption. Therefore, the target block cipher must be secure for the side-channel attacks. However, to recover the 128-bit secret key of the targer block cipher, this attack requires only one random byte fault and an exhausted search of $2^8$. This is the first known cryptanalytic result on the target block cipher.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.5
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• pp.157-163
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• 2017

The binary and interpolation search algorithms are the most famous among search area algorithms, the former running in $O(log_2n)$ on average, and the latter in $O(log_2log_2n)$ on average and O(n) at worst. Also, the interpolation search use only the probability of key value location without priori information. This paper proposes another search algorithm, which I term a 'hybrid block and interpolation search'. This algorithm employs the block search, a method by which MSB index of a data is determined as a block, and the interpolation search to find the exact location of the key. The proposed algorithm reduces the search range with priori information and search the reduced range with uninformed situation. Experimental results show that the algorithm has a time complexity of $O(log_2log_2n_i)$, $n_i{\simeq}0.1n$ both on average and at worst through utilization of previously acquired information on the block search. The proposed algorithm has proved to be approximately 10 times faster than the interpolation search on average.

• Convergence Security Journal
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• v.20 no.1
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• pp.9-14
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• 2020

There have been many papers on minimalism of cryptography. Secure minimal block cipher is one of these topics and Even and Mansour suggested a simple block cipher. The Even-Mansour scheme is a block cipher with one permutation and two whitening keys. Studying related to the Even-Mansour scheme gives great insight into the security and design of block cipher. There have been suggested many trials to analyze the security of the Even-Mansour scheme and variants of the Even-Mansour scheme. We present a new variant of the Even-Mansour scheme and introduce a variant of the Even-Mansour scheme. We focus on the security of these variants of the Even-Mansour scheme and present variation of the security according to key size. We prove the security of a variant of the Even-Mansour scheme and show that a generalized Even-Mansour scheme is not proper for a minimal block cipher.

• ETRI Journal
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• v.43 no.6
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• pp.1113-1129
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• 2021

Lightweight ciphers are increasingly employed in cryptography because of the high demand for secure data transmission in wireless sensor network, embedded devices, and Internet of Things. The PRESENT algorithm as an ultralightweight block cipher provides better solution for secure hardware cryptography with low power consumption and minimum resource. This study generates the key using key rotation and substitution method, which contains key rotation, key switching, and binary-coded decimal-based key generation used in image encryption. The key rotation and substitution-based PRESENT architecture is proposed to increase security level for data stream and randomness in cipher through providing high resistance to attacks. Lookup table is used to design the key scheduling module, thus reducing the area of architecture. Field-programmable gate array (FPGA) performances are evaluated for the proposed and conventional methods. In Virtex 6 device, the proposed key rotation and substitution PRESENT architecture occupied 72 lookup tables, 65 flip flops, and 35 slices which are comparably less to the existing architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1608-1616
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• 2015

This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.

• Journal of Korea Multimedia Society
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• v.7 no.12
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• pp.1719-1728
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• 2004

The fusion of Internet technology and applications with wireless communication provides a new business model and promises to extend the possibilities of commerce to what is popularly called mobile commerce, or m-commerce. In mobile Internet banking service through wireless local area network, security is a most important factor to consider. We describe the development of security service for mobile Internet banking on Personal Digital Assistants (PDAs). Banking Server and Authentication Server were developed to simulate banking business and to support certificate management of authorized clients, respectively. To increase security, we took hybrid approach in implementation: symmetric block encryption and public-key encryption. Hash function and random number generation were exploited to generate a secret key. The data regarding banking service were encrypted with symmetric block encryption, RC4, and the random number sequence was done with public-key encryption. PDAs communicate through IEEE 802.IIb wireless LAN (Local Area Network) to access banking service. Several banking services and graphic user interfaces, which emulatedthe services of real bank, were developed to verity the working of each security service in PDA, the Banking Server, and the Authentication Server.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.263-266
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• 2012

This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.585-592
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• 2014

In this paper, we study the LEA[1] block cipher system in UICC-16bit only. Also, we explain a key-schedule function and encryption/decryption structures, propose an advanced modified key-scheduling, and perform LEA in UICC-16bit that we proposed advanced modified key-scheduling. Also, we compare LEA with ARIA that proposed domestic standard block cipher, and we evaluate the efficiency on the LEA algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.1
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• pp.99-107
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• 2005

ARIA is a 128-bit block cipher having 128-bit, 192-bit, or 256-bit key length. The cipher is a substitution and permutation encryption network (SPN) and uses an involutional binary matrix. This structure was efficiently developed into light weight environments or hardware implementations. This paper shows that a careless implementation of an ARIA on smartcards is vulnerable to a differential power analysis attack This attack is realistic because we can measure power consumption signals at two kinds of S-boxes and two types of substitution layers. By using the two round key, we extracted the master key (MK).