• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.749-757
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• 2015

As the smart era, the use of smart devices is increasing. Smart devices are widely used to provide a human convenience, but there is a risk that information is exposed. The smart devices to prevent this problem includes the encryption algorithm. Among them, The hash function is an encryption algorithm that is used essentially to carry out the algorithm, such as data integrity, authentication, signature. As the issue raised in the collision resistance of SHA-1 has recently been causing a safety problem, and SHA-1 hash function based on the current standard of SHA-2 would also be a problem in the near future safety. Accordingly, NIST selected KECCAK algorithm as SHA-3, it has become necessary to implement this in various environments for this algorithm. In this paper, implementation of KECCAK algorithm. And SHA-2 On The ARM-11 processor, and compare performance.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.9
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• pp.2388-2404
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• 2012

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

• Journal of KIISE
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• v.41 no.11
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• pp.885-891
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• 2014

A hash function is an essential cryptographic algorithm primitive that is used to provide integrity to many applications such as message authentication codes and digital signatures. In this paper, we introduce a concept and test method for a Cryptographic Algorithm Validation Program (CAVP). Also, we design an SHA-3 CAVP program and implement an SHA-3 algorithm in 16bit-UICC. Finally, we compare the efficiency of SHA-3 with SHA-2 and evaluate the exellence of the SHA-3 algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.187-189
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• 2018

In this paper, the optimal design conditions for hardware implementation of the Secure Hash Algorithm3-512 (SHA3-512) hash function were analyzed. Five SHA3-512 hash cores with data-path of 64-bit, 320-bit, 640-bit, 960-bit, and 1600-bit were designed, and their functionality were verified by RTL simulation. Based on the results synthesized with Xilinx Virtex-5 FPGA device, we evaluated the performance of the SHA3-512 hash cores, including maximum frequency, throughput, and occupied slices. The analysis results show that the best hardware performance of SHA3-512 hash core can be achieved by designing it with 1600-bit data-path.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.1
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• pp.31-39
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• 2016

Hash function is a cryptographic primitive which conduct authentication, signature and data integrity. Recently, Wang et al. found collision of standard hash function such as MD5, SHA-1. For that reason, National Security Research Institute in Korea suggests a secure structure and efficient hash function, LSH. LSH consists of three steps, initialization, compression, finalization and computes hash value using addition in modulo $2^W$, bit-wise substitution, word-wise substitution and bit-wise XOR. These operation is parallelizable because each step is independently conducted at the same time. In this paper, we analyse LSH structure and implement it over SIMD-SSE, AVX and demonstrate the superiority of LSH.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.