• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.276-283
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• 2005

Magnetic tunneling transistor (MTT) device using the amorphous n-type Si semiconductor film for base and collector consisting of the [CoFe/NiFe](free layer) and Si(top layer) multilayers was used to study the spin-dependent hot electron magnetocurrent (MC) and tunneling magnetoresistance (TMR) at room temperature. A large MC of 40.2 % was observed at the emitter-base bias voltage ( $V_{EB}$ ) of 0.62 V. The increasing emitter hot current and transfer ratio ( $I_{C}$/ $I_{E}$) as $V_{EB}$ are mainly due to a rapid increase of the number of conduction band states in the Si collector. However, above the $V_{EB}$ of 0.62 V, the rapid decrease of MC was observed in amorphous Si-based MTT because of hot electron spin-dependent elastic scattering across CoFe/Si interfaces.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.133-133
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• 1999

We have fabricated and tested a simple circuit of the rapid single-flux-quantum(RSFQ) four-stage shift register using a single layer high-T$_c$ superconducting (HTS) YBa$_2Cu_3O_{7-x}$ (YBCO) thin film structure with 9 step-edge Josephson junctions. The circuit includes two read superconducting quantum interference devices(SQUID) and four stages. To establish a robust HTS RSFQ device fabrication process, we have focussed the reproducible process of sharp and straight step-edge formation as well as the ratio of film thickness to step height t/h. The spread of step-edge junction parameters was measured from each13 junctions with t/h=l/3, l/2, and 2/3 at various temperatures. We have demonstrated the simplified operation of the shift register at 65 K..

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1286-1293
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• 1988

A general closed form expression for the channel length of the self-aligned double-diffused MOS transistor is obtained from the 2-dimensional Gaussian doping profile. The proposed model in this paper is composed of the doping concentration of the substrate, the final surface doping concentration and the vertical junction depth of the each double-diffused region. The calculated channel length is in good agreement with the experimental results. Also, the optimum channel structure for the prevention of the channel puncthrough is obtained by the averaged doping concentration in the channel region. A correspondence between the results of device simulation of channel punchthrough and the estimations of simplified model is confirmed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.176-184
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• 1996

To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

• The korean journal of orthodontics
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• v.42 no.3
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• pp.110-117
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• 2012

Objective: In this study, we measured the cortical bone thickness in the mandibular buccal and lingual areas using computed tomography in order to evaluate the suitability of these areas for application of temporary anchorage devices (TADs) and to suggest a clinical guide for TADs. Methods: The buccal and lingual cortical bone thickness was measured in 15 men and 15 women. Bone thickness was measured 4 mm apical to the interdental cementoenamel junction between the mandibular canine and the 2nd molar using the transaxial slices in computed tomography images. Results: The cortical bone in the mandibular buccal and lingual areas was thicker in men than in women. In men, the mandibular lingual cortical bone was thicker than the buccal cortical bone, except between the 1st and 2nd molars on both sides. In women, the mandibular lingual cortical bone was thicker in all regions when compared to the buccal cortical bone. The mandibular buccal cortical bone thickness increased from the canine to the molars. The mandibular lingual cortical bone was thickest between the 1st and 2nd premolars, followed by the areas between the canine and 1st premolar, between the 2nd premolar and 1st molar, and between the 1st molar and 2nd molar. Conclusions: There is sufficient cortical bone for TAD applications in the mandibular buccal and lingual areas. This provides the basis and guidelines for the clinical use of TADs in the mandibular buccal and lingual areas.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.377-377
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• 2014

We demonstrate the high temperature-dependent electrical behavior at 2D multilayer MoS2 transistor. Our previous reports explain that the extracted field-effect mobility of good device was inversely proportional to the increase of temperature. Because scattering mechanism is dominated by phonon scattering at a well-designed MoS2 transistor, having, low Schottky barrier. However, mobility at an immature our $MoS_2$ transistor (${\mu}m$ < $10cm^2V^{-1}s^{-1}$) is proportional to the increase temperature. The existence of a big Schottky barrier at $MoS_2-Ti$ junction can reduce carrier transport and lead to lower transistor conductance. At high temperature (380K), the field-effect mobility of multilayer $MoS_2$ transistor increases from 8.93 to $16.9cm^2V^{-1}sec^{-1}$, which is 2 times higher than the value at room temperature. These results demonstrate that carrier transport at an immature $MoS_2$ with a high Schottky barrier is mainly affected by thermionic emission over the energy barrier at high temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.481.2-481.2
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• 2014

Bulk hetero junction (BHJ) polymer solar cell (PSCs) is one of the most promising fields as alternative energy source. Especially, the development of new p-type conjugated polymer is one of the main issues to get core technology. In this study, we investigated the chemical doping effects of incorporating 3,6-carbazole units into conjugated polymers based on 2,7-carbazole. We assessed the structural effects of this chemical doping by measuring the photovoltaic device performance of the copolymers with and without annealing. Note that the use of nanostructures in the bulk heterojunction layer could be a major obstacle to commercialization because nano-morphologies are frequently unstable at high temperatures. Therefore, the development of thermally stable polymer:fullerene blends with optimized PCEs is an important goal in this area of research. We studied the morphologies of the copolymers incorporating 3,6-carbazole units resulting from thermal annealing to investigate the effects of the difference between the T g values of the 2,7-carbazole unit and the 3,6-carbazole unit.

• Korean Journal of Materials Research
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• v.26 no.11
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• pp.635-643
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• 2016

Graphene has shown exceptional properties for high performance devices due to its high carrier mobility. Of particular interest is the potential use of graphene nanoribbons as field-effect transistors. Herein, we introduce a facile approach to the fabrication of graphene nanoribbon (GNR) arrays with ~200 nm width using nanoimprint lithography (NIL), which is a simple and robust method for patterning with high fidelity over a large area. To realize a 2D material-based device, we integrated the graphene nanoribbon arrays in field effect transistors (GNR-FETs) using conventional lithography and metallization on highly-doped $Si/SiO_2$ substrate. Consequently, we observed an enhancement of the performance of the GNR-transistors compared to that of the micro-ribbon graphene transistors. Besides this, using a transfer printing process on a flexible polymeric substrate, we demonstrated graphene-silicon junction structures that use CVD grown graphene as flexible electrodes for Si based transistors.