• Journal of Power Electronics
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• v.14 no.5
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• pp.989-999
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• 2014

High-performance Current Source Inverter (CSI)-fed, variable speed alternating current drives are prepared for various industrial applications. CSI-fed Induction Motor (IM) drives are managed by using different control methods. Noteworthy methods include scalar Control (V/f), Input-Output Linearization (IOL) control, Field-Oriented Control (FOC), and Direct Torque Control (DTC). The objective of this work is to compare the dynamic performance of the aforementioned drive control methods for CSI-fed IM drives. The dynamic performance results of the proposed drives are individually analyzed through sensitivity tests. The tests selected for the comparison are step changes in the reference speed and torque of the motor drive. The operation and performance of different vector control methods are verified through simulations with MATLAB/Simulink and experimental results.

• Journal of Power Electronics
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• v.14 no.5
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• pp.1000-1007
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• 2014

This paper proposes an on-line rotor time constant estimation strategy for indirect field oriented induction machines. The performance of the indirect field oriented control is dependent especially on the rotor time constant whose value varies according to the temperature. The proposed method calculates the difference between the nominal rotor time constant and the real value from the d- and q-axis integration terms of a proportional integral (PI) current regulator and the demanded voltages of the induction machine to regulate the current in the steady state. Because the proposed strategy has a simple structure and is available in wide speed and torque ranges, the proposed method can be easily used in the industrial field. The effectiveness of proposed strategy is verified with simulations and a 7.5kW experimental setup.

• Journal of Power Electronics
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• v.14 no.5
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• pp.937-945
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• 2014

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.

• Journal of Power Electronics
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• v.14 no.5
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• pp.926-936
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• 2014

A simplified and effective space vector pulse-width modulation (SVPWM) algorithm with two and three levels for three-phase voltage-source converters is proposed in this study. The proposed SVPWM algorithm only uses several linear calculations on three-phase modulated voltages without any complicated trigonometric calculations adopted by conventional SVPWM. This simplified SVPWM also avoids choosing the vector sector required by conventional SVPWM. A two-level overmodulation scheme is integrated into the proposed two-level SVPMW to generate the output voltage that increases from a linear region to a six-step state with a smoothly linear transition characteristic and a simple overmodulation process without a lookup table and complicated nonlinear functions. The three-level SVPWM with a proportional-integral controller effectively balances the neutral point potential of the neutral point clamped converter. Results from the simulation in MATLAB/Simulink and the experiment based on a digital signal processor are provided to clearly demonstrate the validity and effectiveness of the proposed strategies.

• Journal of Power Electronics
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• v.14 no.5
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• pp.918-925
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• 2014

This study presents an extended boost single-phase qZ-source DC-AC inverter for a single-phase photovoltaic system. Unlike the previously proposed single-phase qZ-source and semi-qZ-source inverters that achieve the same output voltage as that of the traditional voltage-fed full-bridge inverter, the proposed inverter can obtain higher output than input voltage. The proposed inverter also shares a common ground between DC input voltage and AC output voltage. Thus, possible ground leakage current problem in non-isolated grid-tied inverters can be eliminated with the proposed inverter. A 120 W prototype inverter is built and tested to verify the performance of the proposed inverter.

• Journal of Power Electronics
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• v.14 no.5
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• pp.899-907
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• 2014

This paper proposes a single-phase bidirectional AC/DC converter topology applied in V2G systems, which consists of an inverter and a bidirectional non-inverting buck-boost converter. This topology can operate in four modes: buck charging, boost charging, buck discharging and boost discharging with high input current quality and unity input power factor. The inverter switches at line frequency, which is different from conventional voltage source inverters. A bidirectional buck-boost converter is utilized to adapt to a wider charging voltage range. The modulation and control strategy is introduced in detail, and the switching patterns are optimized to reduce the current ripple. In addition, the semiconductor losses are analyzed. Simulation and experimental results demonstrate the validity and effectiveness of the proposed topology.

• Journal of Power Electronics
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• v.13 no.1
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• pp.161-169
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• 2013

This paper proposes a novel control strategy for a unified power quality conditioner (UPQC) including a series and a shunt active power filter (APF) to compensate the harmonics in both the distorted supply voltage and the nonlinear load current. In the series APF control scheme, a proportional-integral (PI) controller and a resonant controller tuned at six multiples of the fundamental frequency of the network ($6{\omega}_s$) are performed to compensate the harmonics in the distorted source. Meanwhile, a PI controller and three resonant controllers tuned at $6n{\omega}_s$(n=1, 2, 3) are designed in the shunt APF control scheme to mitigate the harmonic currents produced by nonlinear loads. The performance of the proposed UPQC is significantly improved when compared to that of the conventional control strategy thanks to the effective design of the resonant controllers. The feasibility of the proposed UPQC control scheme is validated through simulation and experimental results.

• Journal of Power Electronics
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• v.13 no.1
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• pp.104-112
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• 2013

This paper presents a comparative evaluation of various topologies for three-phase power converters using the hardware-in-the-loop (HIL) simulation technique. Various switch-mode AC-DC power converters are studied, and their performance with respect to total harmonic distortion (THD), efficiency, power factor and losses are analyzed. The HIL-simulation is implemented in an Altera Cyclone II DE2 Field Programmable Gate Array (FPGA) Board and in the Matlab/Simulink environment. A comparison of the simulation and HIL-simulation results is also provided.

• Journal of Power Electronics
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• v.13 no.1
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• pp.113-121
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• 2013

This paper introduces a simple core loss calculation method for output filter inductor in pulse width modulation (PWM) DC-AC inverter. Amorphous C-core (AMCC-320) is used to analyze the core loss. In order to measure core loss of the output filter inductor and validate the proposed method, a single-phase half-bridge inverter and a calorimeter are used. By changing switching frequency and modulation index (MI) of the inverter, core loss of the AMCC-320 is measured with the lab-made calorimeter and the results are compared with calculated core loss. The proposed method can be easily extended to other core loss calculation of various converters.

• Journal of Power Electronics
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• v.13 no.1
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• pp.86-93
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• 2013

A half-cycle-waveform inversion based three reference modulations seven-level SPWM (TRM-SPWM) scheme with one carrier is proposed in this paper. To keep the same comparison logics for the modulations and carrier during the negative half cycle and the positive one for the modulations, in the negative half cycle of the modulations, the DC offsets related to the amplitude of the carrier are set on the three modulations, respectively. The seven-level SPWM waveform with dead time thereby is implemented with only one Digital Signal Processor (DSP) without any other attached logic circuit. The basis principle of the proposed TRM-SPWM is analyzed in detail, and the frequency spectrums of the conventional and the proposed schemes are derived and compared with each other through simulation. The DSP based implementation is presented and detailed experimental waveforms verify the accuracy and feasibility of the proposed TRM-SPWM scheme.