• Title/Summary/Keyword: Is-Spice

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A Novel a-Si TFT Backplane Pixel Structure Using Bootstrapped Voltage Programming of AM-OLED Displays

  • Pyon, Chang-Soo;Ahn, Seong-Jun;Kim, Cheon-Hong;Jun, Jung-Mok;Lee, Jung-Yeal
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.898-901
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    • 2005
  • We propose a novel pixel structure using bootstrapped voltage programming for amorphoussilicon TFT backplane of AM-OLED (Active Matrix-Organic Light Emitting Diode) displays. The proposed structure is composed of two TFTs and one capacitor. It operates at low drive voltage ($0{\sim}5V$) which can reduce power consumption comparing with the conventional pixel circuit structure using same OLED material. Also, it can easily control dark level and use commercial mobile LCD ICs. In this paper, we describe the operating principle and the characteristics of the proposed pixel structure and verify the performance by SPICE simulation comparing with the conventional pixel structure.

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On the detection of short faults in BiCMOS circuits using current path graph (전류 경로 그래프를 이용한 BiCMOS회로의 단락고장 검출)

  • 신재흥;임인칠
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.2
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    • pp.184-195
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    • 1996
  • Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

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Modeling of Arbitrary Shaped Power Distribution Network for High Speed Digital Systems

  • Park, Seong-Geun;Kim, Jiseong;Yook, Jong-Gwan;Park, Han-Kyu
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2002.11a
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    • pp.324-327
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    • 2002
  • For the characterization of arbitrary shaped printed circuit board, lossy transmission line grid model based on SPICE netlist and analytical plane model based on the segmentation method are proposed in this paper. Two methods are compared with an arbitrary shaped power/ground plane. Furthermore, design considerations for the complete power distribution network structure are discussed to ensure the maximum value of the PDN impedance is low enough across the desired frequency range and to guide decoupling capacitor selection.

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Analog MOS circuits for motion detection based on correlation neural networks (상호연관 신경망에 기반을 둔 이동 검출을 위한 아날로그 집적회로)

  • ;;;Masahiro Ohtani;Hiroo Yonezu
    • Proceedings of the IEEK Conference
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    • 2000.11c
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    • pp.149-152
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    • 2000
  • We propose simple analog MOS circuits producing the one-dimensional compact motion-sensing circuits. In the proposed circuit, the optical flow is computed by a number of local motion sensors which are based on biological motion detectors. Mimicking the structure of biological motion detectors made the circuit structure quite simple, compared with conventional velocity sensing circuits. Extensive simulation results by a simulation program of integrated circuit emphasis (SPICE) indicated that the proposed circuits could compute local velocities of a moving light spot and showed direction selectivity for the moving spot

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A data structure and algorithm for MOS logic-with-timing simulation (MOS 로직 및 타이밍 시뮬레이션을 위한 데이타구조 및 알고리즘)

  • 공진흥
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.6
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    • pp.206-219
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    • 1996
  • This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

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Gas Chromatographic Analysis and Cholinesterase Activity of the Essential Oil from Korean Agastache rugosa (기체크로마토그래피에 의한 한국산 배초향의 정유 분석과 Cholinesterase 억제활성)

  • Choi, Jae Sue;Song, Byong-Min;Park, Hee-Juhn
    • Korean Journal of Pharmacognosy
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    • v.47 no.2
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    • pp.192-196
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    • 2016
  • The herb of Agastache rugosa (Lamiaceae) called Korean mint as a spice or Agastache Herba as a crude drug is known to contain highly fragrant volatile substances. This research aimed to establish the quantitative gas chromatography (GC) method on the essential oil of A. rugosa using the three standard compounds, estragole, methyleugenol, pulegone, and to find whether the essential oil has anti-Alzheimer's activity. The GC quantification method was established by determining the linearity of calibration curve ($R^2$), linear range, and both limit-of-detection (LOD) and limit-of-quantification (LOQ). The $IC_{50}$ of the essential oil on the activities of acetylcholinesterase (AChE) and butyrylcholinesterase (BChE) were determined to be $69.06{\pm}0.26$ and $76.71{\pm}0.58{\mu}g/ml$, respectively.

Signal Transient and Crosstalk Model of Capacitively and Inductively Coupled VLSI Interconnect Lines

  • Kim, Tae-Hoon;Kim, Dong-Chul;Eo, Yung-Seon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.4
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    • pp.260-266
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    • 2007
  • Analytical compact form models for the signal transients and crosstalk noise of inductive-effect-prominent multi-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms of the equivalent transmission line model and transmission line parameters for fundamental modes. The signal transients and crosstalk noise expressions of two coupled lines are derived by using a waveform approximation technique. It is shown that the models have excellent agreement with SPICE simulation.

A Study on the Plan Composition of the Super Hire-Rise Apartment - Focused on 20 Cases in Seoul and Kyunggi area - (초고층아파트의 평면구성 특성에 관한 연구 - 서울 및 수도권의 20개 사례를 중심으로 -)

  • 심영섭;김두식
    • Korean Institute of Interior Design Journal
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    • no.41
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    • pp.112-120
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    • 2003
  • The purpose of this study is to review the plan composition characteristics of the super high-rise apartment. 20 cases were selected in Seoul and Kyunggi area that were planned or constructed since 1999, and 10 unit plans were analyzed to review such design characteristics as block type & entry access type, plane figure, opening layout, area distribution and spice composition of unit plan. The result of the study shows that the super high-rise apartment has more variant block types and plane figures compare with the conventional high-rise apartment, and it also has several design characteristics in plane composition such as the increase of the number of the walls with openings, the weakening of the spatial centralization of a living room and the dispersion of rooms with the increase of connection by corridors.

Research on a Streamlined Software Project Management Model for Small-sized Software Enterprises (소규모 소프트웨어 업체를 위한 간략화 된 프로젝트 관리 모델에 관한 연구)

  • Lee, Jeong-Eun;Park, Ju-Chull
    • IE interfaces
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    • v.21 no.2
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    • pp.198-208
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    • 2008
  • Effective management of a project is a crucial issue to software companies. There are various international standards, such as CMM, ISO9000, and SPICE, applied to project management. But, small scale companies have some difficulties in accepting those standards because of its complexity and enormous manpower requirements. This study proposes a project management approach streamlining the CMM by which a small scale software company can perform the tasks with ease. A prototype system has also been developed to show the capability of the proposed model.

Modeling of Electrical Characteristics in Poly Silicon Thin Film Transistor with Process Parameter (다결정 실리콘 박막 트랜지스터에서 공정 파라미터에 따른 전기적 특성의 모델링)

  • Jung, Eun-Sik;Choi, Young-Sik;Lee, Yong-Jae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11b
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    • pp.201-204
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    • 2001
  • In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values, So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of $I_D-V_D$ $I_D-V_G$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.

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