• Bulletin of the Korean Mathematical Society
• /
• v.44 no.2
• /
• pp.233-239
• /
• 2007

Let $\mathbb{A}=\mathbb{F}_q$[T] be the polynomial ring over a finite field $\mathbb{F}_q$[T] and K=$\mathbb{F}_q$(T) its field of fractions. Let ${\ell}$ be a fixed prime divisor of q-1. Let J be a finite set of monic irreducible polynomials $P{\in}{\mathbb{A}}$ with deg $P{\equiv}0$ (mod ${\ell})$. In this paper we define the group $C_K$ of circular units in K=k$(\{\sqrt[{\ell}]P\;:\;P{\in}J\})$ in the sense of Kucera [4] and compute the index of $C_K$ in the full unit group $O^*_K$.

• Proceedings of the IEEK Conference
• /
• 2002.06e
• /
• pp.79-82
• /
• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials in existence coefficients over finite field GF(3$^{m}$ ). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of (m+1)$^2$identical cells, each cell consists of single mod(3) additional gate and single mod(3) multiplicative gate. Proposed multiplier need single mod(3) multiplicative gate delay time and m mod(3) additional gate delay time not clock. Also, the proposed architecture is simple, regular and has the property of modularity, therefore well-suited for VLSI implementation.

• Korean Journal of Mathematics
• /
• v.19 no.4
• /
• pp.403-407
• /
• 2011

In this paper, we study Noetherian Boolean rings. We show that if R is a Noetherian Boolean ring, then R is finite and $R{\simeq}(\mathbb{Z}_2)^n$ for some integer $n{\geq}1$. If R is a Noetherian ring, then R/J is a Noetherian Boolean ring, where J is the intersection of all ideals I of R with |R/I| = 2. Thus R/J is finite, and hence the set of ideals I of R with |R/I| = 2 is finite. We also give a short proof of Hayes's result : For every polynomial $f(x){\in}\mathbb{Z}[x]$ of degree $n{\geq}1$, there are irreducible polynomials $g(x)$ and $h(x)$, each of degree $n$, such that $g(x)+h(x)=f(x)$.

• Journal of the Korean Mathematical Society
• /
• v.57 no.4
• /
• pp.1019-1030
• /
• 2020

Efficient computation of r-th root in 𝔽_q has many applications in computational number theory and many other related areas. We present a new r-th root formula which generalizes Müller's result on square root, and which provides a possible improvement of the Cipolla-Lehmer type algorithms for general case. More precisely, for given r-th power c ∈ 𝔽_q, we show that there exists α ∈ 𝔽_q^r such that $$Tr{\left(\begin{array}{cccc}{{\alpha}^{{\frac{({\sum}_{i=0}^{r-1}\;q^i)-r}{r^2}}}\atop{\text{ }}}\end{array}\right)}^r=c,$$ where $Tr({\alpha})={\alpha}+{\alpha}^q+{\alpha}^{q^2}+{\cdots}+{\alpha}^{q^{r-1}}$ and α is a root of certain irreducible polynomial of degree r over 𝔽_q.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.282-284
• /
• 1988

In this paper, a method for constructing parallel-in, parallel-out multipliers in GF($2^{m}$) is presented. The proposed system is composed of two operational parts by using shift register. One is a multiplicative arithmetical operation part capable of the multiplicative arithmetic and modulo 2 operation to all product terms with the same degree. And the other is an irreducible polynomial operation part to outputs from the multiplicative arithmetical operation part. Since the total hardware is linearly m dependant to an GF($2^{m}$), this system has a reasonable merit when m increases. And also this system is suited for VLSI implementation due to simple, regular, and concurrent properties.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.318-321
• /
• 2000

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.856-859
• /
• 2005

This paper presents a method of constructing the highly efficiency arithmetic operation unit systems(AOUS) based on fields. The proposed AOUS is more regularity and extensibility than previous methods. Also, the proposed AOUS be able to apply basic multimedia hardware. The future research is demanded to more compact and advanced arithmetic operation algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.261-264
• /
• 2005

선진국들은 공모 사업을 통해 많은 블록 암호가 개발되었으나 국내에서 개발된 블록 암호들은 크게 주목 받지 못했다. 블록 암호 개발은 기본의 암호와 차별성, 안전성 그리고 여러 플랫폼에서의 효율성이 중시되는데 이러한 조건을 다 만족하는 것은 쉽지 않기 때문이다. 본 논문은 128bit 블록 단위에서 128, 196, 256bit 키를 사용하는 새로운 블록 암호 알고리즘을 제안한다. 기존의 블록 암호 알고리즘은 SPN(Substitution-Permutation Network)구조, Feistel Network구조 등인데 본 논문에서 제안한 블록 암호 알고리즘은 변형된 Feistel Network구조로 입력 값 전체에서 선택된 32bit 만 update된다. 이러한 구조적 특성은 기존은 블록 암호 알고리즘들과 큰 차별이 되고 있다. PKC블록 암호 알고리즘은 국제 표준 블록 암호 알고리즘인 AES와 국내 표준 블록 암호 알고리즘인 SEED와 수행 속도 면에서 동등하거나 많이 개선된 것을 보이고 있다. 이러한 특성을 이용하면 제한된 환경에서 수행해야 하는 스마트카드 와 같은 분야에 많이 활용 될 수 있을 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.12 no.6
• /
• pp.580-598
• /
• 1987

This paper presents a method to realize the sequential multiple-valued Logic on Galois field. First, We develop so that Taylor series can be corresponded the irreducible polynomial to realize over the finite field, and produce the matrix. This paper object expanded a basic concept of the conbinational Logic circuit so as to apply in the sequential Logic circuit. First of all, We suggest a theory for constructing sequential multiple-valued Logic circuit. Then, We realized the construction with the single input and the multi-output that expanded its function construction. In case of the multi-output, the circuit process by the partition function concept as the mutual independent. This method can be reduced a enormous computer course to need a traditional extention that designed the sequential multi-valued Logic circuit.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.4
• /
• pp.81-87
• /
• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.