• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.112-112
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• 2012

Graphene has been considered as one of the potential post Si-materials due to its high mobility. [1] However, since graphene is semi-conductor with zero band gap, it is difficult to achieve high Ion/Ioff ratio, one of the most important requirements for commercial devices. There have been many attempts to open its band gap for high Ion/Ioff ratio, but most of them end up lowering the mobility. [2-5] Thus, we proposed and demonstrated a new device structure for graphene transistor based on one of the unique properties of graphene for high Ion/Ioff: using this approach, we were able to achieve the ratio over $10^5$. [6] Our device has several major advantages over previously proposed graphene based electronic devices. Since our device does not alter the given properties of graphene, such as opening the band gap, it has no fundamental issues on mobility degradations. In addition, our device is fully compatible with current Si technology and we were able to fabricate the devices with 6 inch wafer scale with CVD (Chemical Vapor Deposition) grown graphene. In this presentation, we will discuss about the details of our graphene device including the device structure and the detailed understanding of working mechanism. We will present device characteristics including I-V curves with $10^5$ on/off ratio. We will also present the performance of an inverter based on our devices. Finally, we will discuss the current issues and their potential solutions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.97-98
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• 2006

For high performance transistor in the 0.14um generation, high speed sram is using a weak region of SCE(Short Channel Effect). It causes serious SCE problem (Vth Roll-Off and Punch-Through etc). This paper shows improvement of Vth roll-off and Ion/Ioff characteristics through high concentration Pocket implant, LDD(Light Dopped Dram) and low energy Implant to reduce S/D Extension resistance. We achieve stabilized Vth and Improved transistor Ion/Ioff performance of 10%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.111-116
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• 2006

In this paper, the image sensor using the a-Si:H TFT is proposed. The optimum amorphous silicon thin film is deposited using plasma enhanced chemical vapor deposition (PECVD). TFT and photodiode both with the thin film are fabricated and form image sensor. The photodiode shows that Idark is $10^{-12}A$, Iphoto is $10^{-9}A$ and Iphoto/Idark is $10^3$, respectively. In the case of a-Si:H TFT, it indicates that Ion/Ioff is $10^6$, the drain current is a few ${\mu}A$ and Vth is $2\~4$ volts. For the analysis on the fabricated image sensor, the reverse bias of -5 voltage in ITO of photodiode and $70{\mu}sec$ pulse in the gate of TFT are applied. The image sensor with good property was conformed through the measured photo/dark current.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1297-1298
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• 2006

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have been attracted recently attention due to their highdevice performance expected from theoretical simulations among nanowire-based FETs with other gate geometries. OSG FETs with the channels of ZnO nanowires were successfully fabricated in this study with photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels of ZnO nanowires with diameters of about 60 nm are coated surroundingly by $Al_{2}O_{3}$ as gate dielectrics with atomic layer deposition. About 80 % of the surfaces of the nanowires coated with $Al_{2}O_{3}$ is covered with gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 98.9 $cm^{2}/Vs$, a peak transconductance of 0.4 ${\mu}S$, and an Ion/Ioff ratio of $10^6$ the value of the Ion/Ioff ratio obtained from this OSG FET is the highest among nanowire-based FETs, to our knowledge. Its mobility, peak transconductance, and Ion/Ioff ratio arc remarkably enhanced by 11.5, 32, and $10^6$ times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1341-1342
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• 2006

Electrical characteristics of field-effect thin film transistors (TFTs) with p-channels of CdTe/CdHgTe core-shell nanocrystals are investigated in this paper. For the fabrication of bottom- and top-gate TFTs, CdTe/CrHgTe nanocrystals synthesized by colloidal method are first dispersed on oxidized p+ Si substrates by spin-coating, the dispersed nanoparticles are sintered at $150^{\circ}C$ to form the channels for the TFTs, and $Al_{2}O_{3}$ layers are deposited on the channels. A representative bottom-gate field-effect TFT with a bottom-gate $SiO_2$ layer exhibits a mobility of $0.21cm^2$/ Vs and an Ion/Ioff ratio of $1.5{\times}10^2$ and a representative top-gate field-effect TFT with a top-gate $Al_{2}O_{3}$ layer provides a field-effect mobility of $0.026cm^2$/ Vs and an Ion/Ioff ratio of $2.5{\times}10^2$. $Al_{2}O_{3}$ was deposited for passivation of CdTe/CdHgTe core-shell nanocrystal layer, resulting in enhanced hole mobility, Ior/Ioff ratio by 0.25, $3{\times}10^3$, respectively. The CdTe/CdHgTe nanocrystal-based TFTs with bottom- and top gate geometries are compared in this paper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.149-150
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• 2006

A ZnO nanowire-based FET is fabricated m this study on a flexible substrate of PES. For the flat and bent flexible substrates, the current ($I_D$) versus drain-source bias voltage ($V_{DS}$) and $I_D$ versus gate voltage ($V_G$) results are compared. The flat band was Ion/Ioff ratio of ${\sim}10^7$, a transconductance of 179 nS and a mobility of ~10.104 cm2/Vs at $V_{DS}$ =1 V. Also bent to a radius curvature of 0.15cm and experienced by an approximately strain of 0.77 % are exhibited an Ion/Ioff ratio of ${\sim}10^7$, a transconductance of ~179 nS and a mobility of ${\sim}10.10 cm^2/Vs$ at $V_{DS}$ = 1V. The electrical characteristics of the FET are not changed very much. although the large strain is given on the device m the bent state.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.1-8
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• 2008

We fabricated flexible electrophoretic display(EPD) driven by organic thin film transistors(OTFTs) on plastic substrate. We designed the W/L of OTFT to be 15, considering EPD's transient characteristics. The OTFTs employed bottom contact structure and used Al for gate electrode, the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. The plastic substrate was coated by PVP barrier layer in order to remove the islands which were formed after pre-shrinkage process and caused the electrical short between bottom scan and top data metal lines. Pentacene active layer was confined within the gate electrodes so that the off current was controlled and reduced by gate electrodes. Especially, PVA/Acryl double layers were inserted between EPD panel and OTFT-backplane in order to protect OTFT-backplane from the damages created by lamination process of EPD panel on the backplane and also accommodate pixel electrodes through via holes. From the OTFT-backplane the mobility was $0.21cm^2/V.s$, Ion/Ioff current ratio $10^5$. The OTFT-EPD panel worked successfully and demonstrated to display some patterns.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.613-613
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• 2013

그래핀은 저차원계 구조에서 기인하는 뛰어난 전기적, 물리적, 기계적 성질을 지니고 있어 실리콘 기반 기술을 대체할 전계 효과 트랜지스터 이외에도 투명전극, 초고용량 커패시터, 전계방출 디스플레이 등 다양한 응용분야에 적용 가능하다. 최근에는 이러한 응용 연구분야에서 그래핀과 탄소나노튜브 각각의 단점을 최소화하고 장점을 극대화하기 위한 그래핀-탄소나노튜브 혼성 나노구조에 대한 연구들이 진행되고 있는 추세이다. 이전 연구들에서 환원된 그래핀 산화물(Reduced Graphene Oxide, RGO)을 이용한 그래핀-탄소나노튜브 혼성 나노구조가 제작되었는데, 이는 RGO의 제작과정에서 복잡한 공정과 긴 합성과정이 요구될 뿐 아니라, 복합 물질에서 탄소나노튜브의 밀도 제어가 어렵다는 단점을 지닌다. 또한 현재까지 제작된 그래핀-탄소나노튜브 혼성 나노구조의 경우, 열 화학기상증착법으로 합성된 다층(few-layers)의 그래핀과 탄소나노튜브 혼성 나노구조를 제작하였다 [1-6]. 본 연구에서는 우수한 전기적 특성을 가진 단층(monolayer)의 그래핀을 열 화학기상증착법으로 합성한 후, 그래핀 위에 단일벽 탄소나노튜브를 성장시킴으로써 그래핀-탄소나노튜브 혼성 나노구조를 제작하였다. 합성된 그래핀-탄소나노튜브의 구조적 특징은 주사 전자 현미경과 라만 분광기 측정을 통해 확인하였고, 촉매의 표면 형상 및 화학적 상태는 원자힘 현미경과 X선 광전자 분광법을 통해 확인하였다. 또한 그래핀 기반의 전계 효과 트랜지스터의 경우, 상온에서 그래핀은 우수한 전하 이동도를 가지며 웨이퍼 스케일에서 제작하기 쉬우나 밴드 갭이 없으므로 높은 Ion/Ioff를 가지는 그래핀 기반의 트랜지스터를 만드는 것이 과제이다. 반면 탄소나노튜브는 큰 에너지 갭을 가지고 있으므로 높은 Ion/Ioff를 구현하는 소자 제작이 가능하다. 그리하여 제작된 그래핀-탄소나노튜브 혼성 나노구조의 소자 제작을 통해 전기적 특성을 조사하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.214.2-214.2
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• 2015

본 연구에서는 Zr을 첨가한 용액 공정 기반 ZTO:Zr 산화물 반도체 제작 및 열처리 온도에 따른 트랜지스터의 특성 변화를 분석하였다. Zn:Sn=4:7 비율로 고정하고, Zr (0~1%) 비율에 따른 도핑과 열처리 온도($350{\sim}550^{\circ}C$)를 가변하였다. 실험 결과, Zr의 비율이 증가할수록 전류와 이동도가 감소하였고, 문턱전압이 양의 방향으로 이동하는 것을 확인하였다. Zr는 SEP (Standard Electrode Potential)가 -1.45로 Zn (-0.76), Sn (-0.13) 보다 작아 금속과 산소의 결합을 증가시키며, 또한 밴드갭이 ~7 eV로 다른 금속 보다 높아 산소와 결합력이 높다. 이러한 요인은 산화물 내의 산소 원자 결함(Oxygen vacancy)을 감소시킨다. 반대로 열처리 온도가 높아질수록 탈 수산화(Dehydroxylation)로 인한 산소 원자 결함이 증가시켜, Zr 도핑 효과와 반대 경향을 보인다. 실험 결과를 통해 Zr:Zn:Sn=0.5:4:7의 비율과 $550^{\circ}C$ 열처리 조건에서 문턱전압과 이동도, 아문턱 스윙, 전류 온오프 비(Ion/Ioff)가 각각 0.68V, $0.18cm^2/Vs$, 1.06 V/dec, $1.6{\times}10.6$의 특성을 확인하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.30.2-30.2
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• 2009

본 연구에서는 stamping법을이용하여 절연막에 실리콘 나노와이어를 embed시킨 field-effect transistor(FET) 소자의 전기적 특성에 대하여 분석하였다. Stamping법은 나노와이어를 이용한 소자를 제작하는데 있어 쉽고 경제적인 방법으로 최근 많이 사용되고 있는데, 이 방법을 이용하여 나노와이어를 절연막에 embed 시켰다. 이때, 사용한 실리콘 나노와이어는 무전해 식각법을 통하여 합성하였다. 식각 시간을 조절하여 나노와이어의 길이가 $100{\mu}m$ 정도가 되도록 하였고, 나노와이어의 지름은 정제를 통하여 20 ~ 200nm내로 조절하였다. FET 소자의 게이트 절연막은가장 일반적으로 사용되는 SiO2 (200nm)와 고분자 절연막으로 잘 알려진 poly-4-vinylphenol(PVP)를 사용하였다. 실리콘 나노와이어의 전기적 특성을 각각 SiO2무기 절연막에서의 non-embedded상태, PVP 유기 절연막에서의 embedded 상태에서 비교분석 하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, threshold voltage값을 평가하였다.