• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.109-116
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• 2021

In this paper, we propose a non-intrusive load monitoring(NILM) system which can find the power of each home appliance from the aggregated total power as the activation in the trading market of the distributed resource and the increasing importance of energy management. We transform the amount of appliances' power into a power on-off state by preprocessing. We use LSTM as a model for predicting states based on these data. Accuracy is measured by comparing predicted states with real ones after postprocessing. In this paper, the accuracy is measured with the different number of electronic products, data postprocessing method, and Time step size. When the number of electronic products is 6, the data postprocessing method using the Round function is used, and Time step size is set to 6, the maximum accuracy can be obtained.

• Journal of Korea Multimedia Society
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• v.19 no.12
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• pp.2014-2023
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• 2016

Web presence is one of the key issues for extensive deployment of Internet-of-Things (IoT). An obstacle to overcome for Web presence is relatively low computing power of IoT devices. In this paper, we present implementation of an IoT platform based on Constrained Application Protocol (CoAP) which is a web transfer protocol proposed by Internet Engineering Task Force (IETF) for the low performance IoT devices such as Wireless Sensor Network (WSN) nodes and micro-controllers. To qualify the performance of CoAP-based IoT system for such an application as smart grid, we designed a test platform consisting of Raspberry Pi2, Kmote WSN node and a desktop PC. Using open source softwares, CoAP was implemented on top of the platform. Leveraging the GET command defined at CoAP specification, performance of the system was measured in terms of round-trip time (RTT) from web application to the Kmote sensor node. To investigate abnormal cases among the test results, hop-by-hop delays were measured to analyze resulting data. The average response time of CoAP-based communication except the abnormal data was reduced by 23% smaller than the previous research result.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.285-287
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• 2014

This paper describes a design of area-efficient/low-power cryptographic processor for lightweight block cipher algorithm HIGHT which was approved as a cryptographic standard by KATS and ISO/IEC. The HIGHT algorithm which is suitable for the security of IoT(Internet of Things), encrypts a 64-bit plain text with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we adopt 32-bit data path and optimize round transform block and key scheduler to share hardware resources for encryption and decryption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.404-406
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• 2015

This paper describes a small-area hardware implementation of the block cipher algorithm CLEFIA-128 which supports for 128-bit master key. A compact structure using single data processing block is adopted, which shares hardware resources for round transformation and the generation of intermediate values for round key scheduling. In addition, data processing and key scheduling blocks are simplified by utilizing a modified GFN(generalized Feistel network) and key scheduling scheme. The CLEFIA-128 crypto-processor is verified by FPGA implementation. It consumes 823 slices of Virtex5 XC5VSX50T device and the estimated throughput is about 105 Mbps with 145 MHz clock frequency.

• Journal of Communications and Networks
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• v.16 no.3
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• pp.344-354
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• 2014

Transmission control protocol friendly rate control (TFRC) is designed to mainly provide optimal service for unicast applications, such as multimedia streaming in the best-effort Internet environment. However, high bandwidth networks with large delays present an environment where TFRC may have a problem in utilizing the full bandwidth. TFRC inherits the slow-start mechanism of TCP Reno, but this is a time-consuming process that may require many round-trip-times (RTTs), until an appropriate sending rate is reached. Another disadvantage inherited from TCP Reno is the RTT-unfairness problem, which severely affects the performance of long-RTT flows. In this paper, we suggest enhanced TFRC for high quality video streaming over high bandwidth delay product networks. First, we propose a fast startup scheme that increases the data rate more aggressively than the slow-start, while mitigating the overshooting problem. Second, we propose a bandwidth estimation method to achieve more equitable bandwidth allocations among streaming flows that compete for the same narrow link with different RTTs. Finally, we improve the responsiveness of TFRC in the presence of severe congestion. Simulation results have shown that our proposal can achieve a fast startup and provide fairness with competing flows compared to the original TFRC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7B
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• pp.653-663
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• 2002

UMTS/GPRS has its own QoS architecture, but additionally needs to support IP-QoS to provide Internet services. This paper describes an IP-QoS provisioning mechanism in the MPLS-based UMTS/GPRS network. We propose a QoS framework that includes the functional architecture of the MPLS-based GPRS networks and the efficient scheduling mechanism based on Diffserv model. The proposed scheduling mechanims is especially focused on the QoS support for real-time services. It also includes a new buffer management scheme that combines the priority queuing and weighted round robin method. The ns-2 simulator has been used to verify the validity of the proposed scheduling method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• The KIPS Transactions:PartC
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• v.12C no.3 s.99
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• pp.437-442
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• 2005

The measurement of RTT (Round Trip Time) can be used for the analysis of Internet congestion. However, simple measuring of RTT which measures only hun around time of a packet can not infer a packet forward/backward delay variation. In this thesis, we present a new algorithm which can be used for the estimation of forward/backward delay variation of packets. These delay variations are implication of network congestion state. In this algorithm, the reference forward/backward delay can be determined based on the minimum RTT value. The delay variation of each packet can be calculated by comparing reference delay with the packet delay. We verified our proposed algorithm by NS-2 simulation and delay measuring in a real network.

• Smart Media Journal
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• v.6 no.3
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• pp.9-14
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• 2017

This paper is a study on the hardware implementation of the encryption and decryption block of the lightweight block cipher algorithm LEA which can be used for tiny devices in IoT environment. It accepts all secret keys with 128 bit, 192 bit, and 256 bit sizes and aims at the integrated implementation of encryption and decryption functions. It describes design results of applying pipeline method for performance enhancement. When a decryption function is executed, round keys are used in reverse order of encryption function. An efficient hardware implementation method for minimizing performance degradation are suggested. Considering the number of rounds are 24, 28, or 32 times according to the size of secret keys, pipeline of LEA is implemented so that 4 round function operations are executed in each pipeline stage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.786-792
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• 2016

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.