• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.76-82
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• 2002

This paper presents a quaternary-binary decoder, a quaternary logic current buffer, and a quaternary logic full-adder using current-mode multiple-valued logic CMOS circuits. Proposed full-adder requires only 15 MOSFET, 60.5% and 48.3% decrease of devices are achieved compared with conventional binary CMOS full-adder and Current's full-adder. Therefore, decrease of area and internal nods are achieved. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 1.5 ns of propagation delay and 0.42㎽ of power consumption. Also, proposed full-adder can easily adapted to binary system by use of encoder, designed decoder and designed current buffer.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.16 no.1
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• pp.27-35
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• 2016

Black-box classifiers, such as artificial neural network and support vector machine, are a popular classifier because of its remarkable performance. They are applied in various fields such as inductive inferences, classifications, or regressions. However, by its characteristics, they cannot provide appropriate explanations how the classification results are derived. Therefore, there are plenty of actively discussed researches about interpreting trained black-box classifiers. In this paper, we propose a method to make a fuzzy logic-based classifier using extracted rules from the artificial neural network and support vector machine in order to interpret internal structures. As an object of classification, an anomalous propagation echo is selected which occurs frequently in radar data and becomes the problem in a precipitation estimation process. After applying a clustering method, learning dataset is generated from clusters. Using the learning dataset, artificial neural network and support vector machine are implemented. After that, decision trees for each classifier are generated. And they are used to implement simplified fuzzy logic-based classifiers by rule extraction and input selection. Finally, we can verify and compare performances. With actual occurrence cased of the anomalous propagation echo, we can determine the inner structures of the black-box classifiers.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.4
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• pp.179-188
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• 2003

Percentage differential characteristic scheme has been recognized as the principal basis for large transformer protection. Nowadays, relaying signals can contain second harmonic component to a large extent even in a normal state, and second harmonic ratio indicates a tendency of relative reduction because of the advancement of transformer's core material. And then, conventional second harmonic restraint differential relaying exposes some doubt in reliability. It is, therefore, necessary to develop a new algorithm for the effective and accurate discrimination. This paper deals with advanced fuzzy logic based relaying by using flux differential, and a new fault detection criterion logic scheme by using wavelet transform. To comparative analysis of proposed techniques, the paper constructs power system model including power transformer, utilizing the EMTP, and collects data through simulation of various internal faults and magnetizing inrush. The proposed fuzzy relaying and a new fault detection scheme were tested. The former, fuzzy relaying, was proven to be faster and more reliable than the latter.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Advances in Computational Design
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• v.5 no.4
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• pp.445-465
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• 2020

This paper presents a study conducted with the aim of developing a model of tendering based on a technique of artificial intelligence by managing and controlling the factors of success or failure of construction projects through the evaluation of the process of invitation to tender. Aiming to solve this problem, analysis of the current environment based on SWOT (Strengths, Weaknesses, Opportunities, and Threats) is first carried out. Analysis was evaluated through a case study of the construction projects in Algeria, to bring about the internal and external factors which affect the process of invitation to tender related to the construction projects. This paper aims to develop a mean to identify threats-opportunities and strength-weaknesses related to the environment of various national construction projects, leading to the decision on whether to continue the project or not. Following a SWOT analysis, novel artificial intelligence models in forecasting the project status are proposed. The basic principal consists in interconnecting the different factors to model this phenomenon. An artificial neural network model is first proposed, followed by a model based on fuzzy logic. A third model resulting from the combination of the two previous ones is developed as a hybrid model. A simulation study is carried out to assess performance of the three models showing that the hybrid model is better suited in forecasting the construction project status than RNN (recurrent neural network) and FL (fuzzy logic) models.

• Aerospace Engineering and Technology
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• v.10 no.1
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• pp.141-148
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• 2011

LEO satellites have many heaters for thermal control, such as bus module heaters, payload heaters and battery internal heaters. Some of these heaters are controlled by thermisters, and others can be controlled by flight software. These heaters are divided into various types of group according to the location, telemetry variables, flight software logic, power distribution, etc. Thus, it is difficult to find out which heaters are included in a certain group and modify heater control logic for a new/other software developers. This document describes about the general/special control logic for satellite heaters and groups/arrays for heaters.

• International Journal of Naval Architecture and Ocean Engineering
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• v.4 no.4
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• pp.362-373
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• 2012

The ship recycling industry is growing rapidly. It is estimated that the International Maritime Organization's (IMO) decision to phase-out single hull tankers by 2015 will result in hundreds of ships requiring disposal. At present, the ship recycling industry is predominantly based in South Asia. Due to the bad practice of current scrapping procedure, the paper will highlight the harm occurring to health, safety and environment. The efforts of the Marine Environment Protection Committee (MEPC) which led to the signing of the Hong Kong International Convention are also reviewed. The criteria and standards required to reduce the risk and damage to the environment are discussed and a proposed plan for the safe scrapping of ships is then presented. A technological and economic study for the ship recycling in Egypt is carried out as a case study. This includes the ship recycling facility size and layout. The equipment and staff required to operate the facility are also evaluated. A cost analysis is then carried out. This includes site development, human resources, machineries and equipment. A fuzzy logic approach is used to assess the benefits of the ship breaking yard. The use of the fuzzy logic approach is found suitable to make decisions for the ship breaking industry. Based on given constraints, the proposed model has proved capable of assessing the profit and the internal rate of return.