• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.514-516
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• 2018

We have investigated the effect of interface trap charge on the characteristics of a monolithic 3D inverter by TCAD simulation. The interface trap charge affects the variation of the threshold voltage and threshold voltage. also The interface trap charge affects the IN/OUT characteristics of the monolithic 3D inverter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.4
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• pp.350-356
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• 2005

We report the space charge and the surface potential of the interface between metal and copper(Ⅱ)-phthalocyanine(CuPc) thin films by measuring the microwave reflection coefficients S/sub 11/ of thin films using a near-field scanning microwave microscope(NSMM). CuPc thin films were prepared on Au and Al thin films using a thermal evaporation method. Two kinds of CuPc thin films were prepared by different substrate heating conditions; one was deposited on preheated substrate at 150。C and the other was annealed after deposition. The microwave reflection coefficients S/sub 11/ of CuPc thin films were changed by the dependence on grain alignment due to heat treatment conditions and depended on thickness of CuPc thin films. Electrical conductivity of interface between metal and organic CuPc was changed by the space charge of the interface. By comparing reflection coefficient S/sub 11/ we observed the electrical conductivity changes of CuPc thin films by the changes of surface potential and space charge at the interface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.526-530
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• 2004

We report the space charge and the surface potential of the interface between metal and CuPc according to isotropic property and different metal by measuring the microwave reflection coefficients $S_{11}$ of copper(II)-phthalocyanine(CuPc) thin films by using a near-field microwave microscope(NSMM) in order to understand. CuPc thin films were prepared on gold and aluminium substrates using a thermal evaporation method. Two kinds of CuPc thin films were prepared. One was deposited on preheated substrate at $150^{\circ}C$ and the other was annealed after deposition by using thermal evaporation methods. The microwave reflection coefficients $S_{11}$ of CuPc thin films were changed by the dependence on the heat treatment conditions. By comparing reflection coefficient $S_{11}$ we measured electrical conductivity of CuPc thin films and studied this results with respect to the surface potential and space charge of the interface between metal and CuPc thin films.

• Journal of the Korean Magnetic Resonance Society
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• v.4 no.2
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• pp.82-90
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• 2000

Photoinduced charge separation of alkylphenothiazines in molecular assemblies such as positively, negatively and neutrally charged micelle interface results in the paramagnetic phenothiazine cation radical. This was studied as a model system for the light energy conversion into chemical energy. The photoproduced phenothaizne cation radical was identified and its amount was quantized with electron spin resonance (ESR). The microenvironment of photoproduced cation radical was studied with pulsed-ESR. Such a charge separation is enhanced by the optimization of various structural factors of the molecular assemblies. The structural factors of molecular assemblies have focused on the interface charge, interface structure with different headgroups and interfacial perturbation by disolving interface active organic additives.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.211-214
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• 1998

DC breakdown characteristics and formation of space charge at the interfaces of crosslinked polyethylene (XLPE) /ethylene propylene diene terpolymer (EPDM) laminates were studied. Effects of silicone grease and some chemicals such as crosslinking coagent on the interfacial charge were also studied. Interfacial charge develops at the interface of XLPE/EPDM laminates, which changes depending on heat treatment conditions and types of chemicals coated at the interface. Some chemicals such as maleic anhydride reduce the accumulation of interfacial charge in the XLPE/EPDM laminates. Breakdown strength of EPDM/XLPE laminate through the interface was highest when silicone oil was pasted in the interfaces. Interfacial breakdown strength decreased with the increase of MAH content.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.328.1-328.1
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• 2014

MOSFET degradation의 대부분은 hot-carrier injection에 의한 interface state (Dit)의 생성에서 비롯되며 따라서 본 연구에서는 신뢰성에 대한 한 가지 방법으로 Charge pumping method를 이용하여 MOSFET의 interface trap(Dit)의 변화를 측정하였다. 소스와 드레인을 ground로 묶고 게이트에 펄스를 인가한 후 Icp를 측정하여 Dit를 추출하였다. 온도를 293~343 K까지 5 K씩 가변했을 때 293K의 Icp(${\mu}A$)는 0.12 nA 313 K는 0.112 nA 343 K는 0.926 nA이며 Dit (cm-1/eV-1)는 $1.61{\times}10^{12}$ (Cm-2/eV-1) $1.49{\times}10^{12}$ (Cm-2/eV-1) $1.23{\times}10^{12}$ (Cm-2/eV-1)이다. 측정결과 Dit는 Icp가 높은 지점에서 추출되며 온도가 높아지게 되면 Icp전류가 낮아지고 Dit가 줄어드는 것을 볼 수 있다. 온도가 올라가게 되면 carrier들이 trap 준위에서 conduction band 위쪽에 이동하게 되어서 interface에 trap되는 양이 작아지게 된다. 그래서 이때 Icp를 이용해 추출한 Dit 는 실제로 trap의 양이 줄어든 것이 아니라 Thermal excess 현상으로 인해 측정되는 Icp의 양이 줄어든 것으로 분석할 수 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.59-64
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• 1994

The Si-SiO$_2$interface trpas of the degraded short-channel SONOSFET memory devices were investigated using the charge pumping techniques. The degradation of devices with write/erase cycle appeared as the increase of the Si-SiO$_2$interface trap density. In order to determine the capture cross-section of the interface trap. I$\_$CP/-V$\_$GL/ characteristic curves were measured at different temperatures. Also, the spatial distributions of Si-SiO$_2$interface trap were examined by the variable-reverse bias boltage method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.