• 한국정밀공학회지
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• 제31권6호
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• pp.469-475
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• 2014

The roll to roll (RTR) imprint process is an integrated imprinting process where steps ranging from assignment of a function to a flexible rolled substrate to rewinding of the same substrate in a roll are performed. RTR imprint is a green, low-cost technology without limitations. In RTR imprint, it is important to manufacture the mold precisely and maintain uniform process condition. To this, process conditions have to include precision tension control, optimization of process parameters. We introduced RTR imprint to fabricate planar lightwave circuit (PLC) device for communication, by new schematic design and process optimization, we fabricated successfully optical device. The fabricated optical device showed the optical performance which was satisfied to meet international standard.

• ETRI Journal
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• 제38권6호
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• 한국전기전자재료학회논문지
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• 제17권2호
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• pp.138-143
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• 2004

CMP (Chemical Mechanical Polishing) technology for global planarization of multilevel interconnection structure has been widely studied for the next generation devices. Among the consumables for CMP process, especially, slurry and their chemical compositions play a very important role in the removal rates and within-wafer non-uniformity (WIWNU) for global planarization ability of CMP process. However, CMP slurries contain abrasive particles exceeding 1 ${\mu}{\textrm}{m}$ size, which can cause micro-scratch on the wafer surface after CMP process. Such a large size particle in these slurries may be caused by particle agglomeration in slurry supply-line. In this work, to investigate the effects of agglomeration on the performance of oxide CMP slurry, we have studied an aging effect of silica slurry as a function of particle size distribution and aging time during one month. We Prepared and compared the self-developed silica slurry by adding of alumina powders. Also, we have investigated the oxide CMP characteristics. As an experimental result, we could be obtained the relatively stable slurry characteristics comparable to aging effect of original silica slurry. Consequently, we can expect the saving of high-cost slurry.

• 산업경영시스템학회지
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• 제34권4호
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• pp.72-81
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• 2011

In this paper, we propose adaptive convergence security policies and management technologies to improve security assurance in the home networking environment. Many security issues may arise in the home networking environment. Examples of such security issues include the user privacy, the service security, the integrated networking security, the middleware security and the device failure. All these security issues, however, should be fulfilled in phase due to many difficulties including deployment cost and technical complexity. For instance, fundamental security requirements such as authentication, access control and prevention of crime and disaster should be addressed first. Then, supplementary security policies and diverse security management technologies should be fulfilled. In this paper, we classify these requirements into three categories, a service authentication, a user authentication and a device authentication, and propose security policies and management technologies for each requirement. Since the home gateway is responsible for interconnection of many home devices and external network access, a variety of context information could be collected from such devices.

• 한국통신학회논문지
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• 제33권5B호
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• pp.356-363
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• 2008

1983년 미국에서 보편적서비스 지원을 위한 기금제도(USF: Universal Service Fund)가 도입된 이래 각국 정부는 저렴한 요금으로 모든 국민들이 기본적인 통신서비스를 제공받을 수 있도록 보편적서비스 지원제도를 운영하고 있다. 국내에서도 2000년 이래 보편적서비스 지원제도가 도입되었고, 최근에 제도개선논의가 활발히 전개되고 있다. 본고에서는 주요국의 보편적서비스 손실금 지원제도를 비교분석하고 국내 제도 개선시 시사점을 찾아보고자 한다.

• 정보처리학회논문지A
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• 제12A권6호
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• pp.499-506
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• 2005

최근에 하이퍼큐브의 망비용을 개선한 하이퍼-스타 연결망 HS(m,k)이 제안되었다. 본 논문에서는 정규연결망 하이퍼-스타 HS(2n,n)의 이분할 에지수가 최대(2n-2,n-1)임을 보이고, 병렬경로 집합을 이용하여 k-광역지름이 dist(u, v)+4이하이고, HS(2n,n)의 고장지름이 D(HS(2n+n))+2 이하임을 보인다. dist(u,v)는 임의의 두 노드 u와 v 사이의 최단 거리를 나타내고, D(HS(2n,n))는 HS(2n,n)의 지름을 나타낸다.

• 융합신호처리학회논문지
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• 제5권3호
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• pp.236-242
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• 2004

본 논문에서는 병렬프로그램을 효율적으로 수행하는데 필수적인 부하분산을 위한 기존 알고리즘의 부하분산 오버헤드를 최소화하기 위하여 이 알고리즘의 병렬화 방법을 제시한다. 병렬계산 모델로는 동적으로 변하는 트리구조를 들었으며 이러한 계산은 많은 응용분야에서 찾아볼 수 있다. 부하분산 알고리즘은 통신비용을 정해진 한도 이내로 유지하면서 프로세서간 계산부하를 최대한 균등하게 분산시키고자 시도한다. 이 알고리즘이 메쉬와 하이퍼큐브 구조에서 어떻게 병렬화 될 수 있는가를 상세히 보이고 각각의 경우에 대하여 시간상 복잡도를 분석하여 기존의 알고리즘보다 여러가지 오버헤드가 개선되었음을 증명한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.321-322
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• 2007

In order to increase the cost effectiveness of solar cells, module production should be treated more comprehensively. Back contact cells offer distinct advantage in the interconnection of cells to modules. Thereby Mo thin film were prepared in order to clarify optimum conditions for growth of the thin film depending upon process, and then by changing a number of deposition conditions and substrate temperature conditions variously, structural and electrical characteristics were measured. For the manufacture of the Mo were vapor-deposited in the named order. Among them, Mo were vapor-deposited by using the sputtering method in consideration of their adhesive force to the substrate, and the DC power was controlled so that the composition of Mo, while the surface temperature having an effect on the quality of the thin film was changed from R.T$[^{\circ}C]$ to $200[^{\circ}C]$ at intervals of $50[^{\circ}C]$. Micro-structural studies were carried out by XRD (D/MAX-1200, Rigaku Co.) and SEM (JSM-5400, Jeol Co.). Electrical properties were measured by CMT-SR3000 Measurement System.

• KEPCO Journal on Electric Power and Energy
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• 제7권1호
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• pp.93-99
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• 2021

The government has proposed a mission to enhance intelligent power networks, decrease coal-fired generation, expand distributed energy resources, and promote energy prosumer into the distribution network in Korea. Installation cost of facility expansion to guaranteed interconnection with small distributed energy resources increases dramatically on KEPCO's distribution sector. And it is hard to withdraw in time. In addition, there are explicit research is required to meet the reliability on grid corresponding to the increase of distributed power. Infrastructure support for accommodating energy prosumer is also needed. Therefore, KEPCO is pushing transition to DSO by expanding distribution management scope and changing its roles. In addition, KEPCO is proactively preparing for integrated operation between distribution network and existing distributed power which is accommodated passively. KEPCO is also trying to accept multiple network users, e.g. building platforms, to manage a data and promote new markets. In the long term, transition to DSO will achieve saving investment costs for accommodating distributed sources and maintaining stable electrical quality. And it will be possible to create new business model using the platform to secure revenue.

• 한국정보과학회논문지:시스템및이론
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• 제27권2호
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• pp.177-187
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• 2000

최근 몇 년간 클리스터링 기반 다중 프로세서 시스템에서의 상호 연결망으로서의 버스의 제약을 극복하기 위한 단방향 지점간 링크를 이용한 링 구조가 제안되었다. 하지만 계속되는 프로세서의 고속화와 지역 버스 및 메모리의 고성능화로 인해 지점간 링크의 현재 표준 대역폭으로는 시스템 확장성에 한계를 보이며 이에 따라 대역폭 확장에 대한 연구가 필요하다. 본 논문에서는 클리스터링 기반 다중프로세서 시스템으로 개발된 PANDA 시스템을 기본 모델로 채택한다. 최근 대중화된 프로세서 및 지역 버스의 사양을 반영한 모의실험을 통해 현재의 지점간 링크가 전체 시스템 성능에 병목이 됨을 보여주고 두 배 이상의 대역폭 확장이 필요함을 보인다. 상호 연결망의 대역폭을 확장하기 위해, 두 배 증가된 대역폭을 지닌 새로운 링크를 개발하는 것은 과다한 설계비용과 개발시간이 요구된다. 이에 대한 대안으로 본 논문에서는 상용화되어있어 쉽게 적용 가능한 기존 IEEE 표준 대역폭을 가진 링크를 이용해 이중으로 링을 구성하는 몇 가지 방법 단순 이중 링, 트랜잭션 분리 이중 링, 방향 분리 이중 링 - 을 제시하고 모의실험을 통해 두 배 대역폭 단일 링과 더불어 각각의 방식에 대한 장단점을 분석한다.