• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.303-310
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• 2006

The sorting algorithms have been developed to take advantage of distributed computers. But the speedup of parallel sorting algorithms decrease rapidly with increased number of processors due to parallel processing overhead such as context switching time and inter-processor communication cost. In this paper, we propose a parallel sorting method which provides linear speedup of an optimal serial algorithm for a system with a large number of processors. This algorithm may even provide superlinear speedup for a practical system. The algorithm takes advantage of an interconnection network properties and its protocol.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.261-271
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• 2008

Holographic volume grating couplers (VGCs) are become increasingly attractive device for the application of optical interconnects because of their higher preferential coupling, dry fabrication processing, compact, and low cost. In this paper, the analysis, design, and implementation of the waveguide-imbedded input-output VGC with $45^{\circ}$ grating slant angle using holographic photopolymer(Dupont HRF600-20) for guided-wave optical interconnection applications, are presented. To show the usefulness of the proposed VGC, we fabricated the VGCs operating at 632.8nm and 1550nm wavelengths and its results are presented. The measured input coupling efficiency of the single VGC with $0.5{\mu}m$ grating period at 632.8nm wavelength is above 86.6% for TE-polarization. The input coupling efficiency of the $1\times2$ VGC with $0.73068{\mu}m$ grating period at 1550nm wavelength is about 90.8%.

• Proceedings of the Korean Professional Engineer Association Conference
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• 1996.12a
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• pp.76-102
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• 1996

북한은 전력부족난과 전기품질의 저하로 인하여 주요 생산기업에 지장을 주고 있으며, 노후 발전소의 성능저하도 함께 진행되고 있는 것으로 추정된다. 이에 대한 적절한 대책이 없는 한 그 상황은 더욱 악화될 전망이다. 한반도 에너지 개발기구(KEDO)가 추진하고 있는 경수로 원자력 발전기가 6～7년 후에 준공된다고 해도 이처럼 불안정한 전력계통에 병입되어 원활한 운전이 가능할런지 기대하기 곤란하다. 이러한 실정에서 \circled1 전력부족으로 주파수가 저하될 때 우선 순위가 낮은 부하를 제한하는 자동 부하제한 방식을 포함한 자동 주파수 제어 계통개선 \circled2 기존발전소 성능과 이용을 향상을 위한 재가동(Repowering) 등의 리 엔지니어링 \circled3 가스터빈 복합화력과 열병합발전(Co-generation) 등과 같이 건설기간이 짧고 비용이 적게 들며 송전 설비 건설도 불필요한 분산형 전원의 건설 \circled4 수력발전소와 조력발전소의 건설 \circled5 양수발전 등 전력에너지 저장설비의 개발 \circled6 송전전압격상과 배전방식개선 및 종합전력정보시스템 구축 \circled7 남ㆍ북한 전력계통 내지는 동북아시아 전력계통을 연계하는 평화망사업(Peace Network Project)등의 추진이 경수로 사업에 선행되어야 한다. 특히 러시아, 중국, 한국, 일본의 발전 에너지원 분포와 년간 부하곡선을 고려할 때 동북아시아 전력계통의 연계는 관련국 상호간에 에너지 환경과 경제적 측면에서 상당한 이득과 안정성을 강화해 줄 것이며, 기술발전과 평화공존에 크게 기여 할 것이다. 이를 위하여 관련국의 전력계통연계 전문가들이 참여하는 남\ulcorner북한전력 계통연계연합회(Co-Pia ; Co-rea Power Systems Interconnection Association)와 동북아지역전력 계통연합회(Near Pia=North-Eastern Asia Region Power Systems Interconnection Association)의 구성을 제안하는 바이다. 주요용어(Key Words): 자동주파수 제어(AFC), 리엔지니어링(Re-Engineering), 분산형 전원(Dispersed Generation System), 전력저장(Power Storage), 부하조절기(Load Conditioner), 수요관리(DSM) 연계(Interconnection), 인터시스템(Intersystem), 통합자원계획(IRP), 안전성 강화(Security Enhancement), 전력시장개방(Electricity Free Maket), 통일비용(Unification Expense, Unification Cost), 남ㆍ북한전력계통연계연합회(Co-Pia), 동북아지역전력 계통연계연합회(Nea,-Pia).

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.35-43
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• 2001

Flip chip assembly on organic substrates using ACAs have received much attentions due to many advantages such as easier processing, good electrical performance, lower cost, and low temperature processing compatible with organic substrates. ACAs are generally composed of epoxy polymer resin and small amount of conductive fillers (less than 10 wt.%). As a result, ACAs have almost the same CTE values as an epoxy material itself which are higher than conventional underfill materials which contains lots of fillers. Therefore, it is necessary to lower the CTE value of ACAs to obtain more reliable flip chip assembly on organic substrates using ACAs. To modify the ACA composite materials with some amount of conductive fillers, non-conductive fillers were incorporated into ACAs. In this paper, we investigated the effect of fillers on the thermo-mechanical properties of modified ACA composite materials and the reliability of flip chip assembly on organic substrates using modified ACA composite materials. Contact resistance changes were measured during reliability tests such as thermal cycling, high humidity and temperature, and high temperature at dry condition. It was observed that reliability results were significantly affected by CTEs of ACA materials especially at the thermal cycling test. Results showed that flip chip assembly using modified ACA composites with lower CTEs and higher modulus by loading non-conducting fillers exhibited better contact resistance behavior than conventional ACAs without non-conducting fillers. Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of $SiO_2filler$ to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. Our results indicate that the electrical performance of ACF combined with electroless Wi/Au bump interconnection is comparable to that of solder joint.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.215-226
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• 2007

For past years, many distributed virtual shared-memory(DVSM) systems have been studied in order to develop a low-cost shared memory system with a fast interconnection network. But the DVSM needs a lot of data and control communication between distributed processing nodes in order to provide memory consistency in software, and this communication overhead significantly dominates the overall performance. In general, the communication overhead also increases as the number of processing nodes increase, so communication overhead is a very important performance factor for developing a large-scale DVSM system. In this paper, we study the performance scalability quantitatively and qualitatively for developing a large-scale DVSM system based on the next generation interconnection network, called the InfiniBand. Based on the study, we analyze a performance requirement of the next-coming interconnection network to be used for developing a performance-scalable DVSM system in the future.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.385-389
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• 2003

There are four main components of the CMP process: polishing pad, slurry, elastic supporter, and pad conditioner. The polishing pad is an essential component to the reproducibility of polishing uniformity in CMP process. However, the polishing pad in recently using metal CMP raised the several points of high cost caused by the increase of cycle time and the many usage of slurry. It is necessary to develop the novel polishing pad which would lead the cost reduction by the higher pad life-cycle, minimized cycle time and lower slurry usage. The characteristics of polishing pad were studied on the effects of different sets of the Polishing pad, which can be applied to metal chemical mechanical polishing process for global planarization of multilevel interconnection structure. The main purpose of this experiment is cost reduction by the increase of pad life-time, the decrease of cycle time and the lower usage of slurry through the specific hard porous structured pad design. It is confirmed that the novel polishing pad made the slurry usage decrease to 60% as well as the pad life-time increase twice with the 25% improvement of removal rate. The polishing time could be decreased and it also helped the cycle time to diminish. It can be expected that this results will help both the process throughput and the device yield to be improved.

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.439-449
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• 2002

This paper reviews our recent research works on the interconnection technologies in electronic packaging and assembly. At the aspect of advanced joining methods, laser-ultrasonic fluxless soldering technology was proposed. The characteristic of this technology is that the oxide film was removed through the vibration excitated by high frequency laser change in the molten solder droplet. Application researches of laser soldering technology on solder bumping of BGA packages were carried out. Furthermore, interfacial reaction between SnPb eutectic solder and Au/Ni/Cu pad during laser reflow was analyzed. At the aspect of soldered joints' reliability, the system for predicting and analyzing SMT solder joint shape and reliability(PSAR) has been designed. Optimization design method of soldered joints' structure was brought forward after the investigation of fatigue failure of RC chip devices and BGA packages under temperature cyclic conditions with FEM analysis and experimental study. At the aspect of solder alloy design, alloy design method based on quantum was proposed. The macroproperties such as melting point, wettability and strength were described by the electron parameters. In this way, a great deal of the experimental investigations was replaced, so as to realize the design and research of any kinds of solder alloys with low cost and high efficiency.

• Journal of Communications and Networks
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• v.8 no.4
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• pp.369-377
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• 2006

Recently, the metropolitan area network (MAN) has attracted much attention in telecommunication research and has emerged as one of the most important research topics in the community. Several standards representing the first step for developing metropolitan networks have been published; IEEE 802.16 (WiMAX) has taken a relevant role in reaching the goal of realizing a full-service network all over a urban and suburban area. At the same time, the wireless local area networks (WLAN) have been widely used for in-home or short range communications, mainly basing on the IEEE 802.11 (WiFi) standard. A consequence is the increasing interest in interworking technology, that allows an interconnection between different standards by maintaining certain properties, mainly in terms of quality of service (QoS). One of the major issues is to design bridging devices capable of transparently interconnect different wireless technologies. In this paper, we propose two interconnection bridging solutions between WiMAX and WiFi links; the first is more based on the concept of maintaining a certain end-to-end QoS level independently from the wireless technologies used. The second method is more devoted to the reduction of the implementation complexity at the cost of no QoS assurance. The performance of the two methods are compared by resorting to computer simulations showing the advantages of each one technique.

• Journal of Korea Multimedia Society
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• v.11 no.9
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• pp.1227-1237
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• 2008

In this paper, we analyze topological properties and embedding of Folded Hyper-Star network to further improve the network cost of Hypercube, a major interconnection network. Folded Hyper-Star network has a recursive expansion and maximal fault tolerance. The result of embedding is that Folded Hypercube $FQ_n$ and $n{\times}n$ Torus can be embedded into Folded Hyper-Star FHS(2n,n) with dilation 2. Also, we show Folded Hyper-Star FHS(2n,n) can be embedded into Folded Hypercube $FQ_{2n-1}$ with dilation 1.