• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.412-415
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• 1999

In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2001.04a
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• pp.61-68
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• 2001

A parallel nonlinear analysis program of prestressed concrete frame is migrated on a PC cluster system and a massively parallel processing system, CRAY T3E system, using MPI. The PC cluster system is configured with Pentium Ⅲ class PCs and fast ethernet. The CRAY T3E system is composed of a set of nodes each containing one Processing Element (PE), a memory subsystem and its distributed memory interconnect network. Parallel computing algorithms are implemented on element-wise processing parts including the calculation of stiffness matrix, element stresses and determination of material states, check of material failure and calculation of unbalanced loads. Parallel performance of the migrated program is evaluated through typical numerical examples.

• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.62-69
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• 2011

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

• ETRI Journal
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• v.39 no.5
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.397-403
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• 2004

The controller area network(CAN) was originally developed to support cheap and rather simple automative applications, However, because of the its performance and low cost, it is also being considered in automated manufacturing and process control environments to interconnect intelligent devices, such as modem sensors and actuators. This paper presents a new application technology of the developed CAN control modules for the automated doors in building automation system. Key pad and RF methods are used to open and close the automated door by the slave CAN module with CAN protocol. BAS application technology of CAN field bus modules is also presented firstly in our nation.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.116-127
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• 1999

Networking for manufacturing is gaining importance as a nerve system of computer-integrated manufacturing (CIM). Among the various network types, the most inexpensive type called fieldbus is specifically aimed to interconnect simple devices such as sensors and actuators. For this purpose, there are several choices of the protocols such as Profibus. WorldFIP, Foundation Fieldbus, and IEC/ISA fieldbus. This paper presents the simulation results of Profibus and WorldFIP. Both protocols have been simulated in order to evaluate the performance such as transmission delay and throughput under different protocol parameter settings and traffic conditions.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.11 no.4
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• pp.1-8
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• 2007

In some wireless sensor networks, the sensor nodes are required to be located sparsely at designated positions over a wide area, introducing the problem of adding minimum number of relay nodes to interconnect the sensor nodes. The problem finds its a bstract form in literature: the Minimum number of Steiner Points. Since it is known to be NP-hard, this paper proposes an approximation scheme to estimate the minimum number of relay nodes through the properties of the abstract form. Note that by reducing the numb er of nodes in a sensor network, the amount of data exchange over the net will be far decreased.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.2
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• pp.364-369
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• 2019

Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.2-4
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• 2023

KISTI의 GPU 클러스터 시스템인 뉴론은 NVIDIA의 A100과 V100 GPU가 총 260개 탑재되어 있는 클러스터 시스템이다. 뉴론의 계산노드들은 고성능의 인터커넥트인 Infiniband(IB) 케이블로 연결되어 있어 멀티 노드 작업 수행 시에 고대역 병렬통신이 가능하다. 본 논문에서는 NVIDIA사에서 제공하는 NCCL의 벤치마크 코드를 이용하여 인터커넥트 네트워크의 통신 성능을 비교분석하는 방안에 대해서 소개한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.