• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1323-1333
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• 1997

In this paper, we propose an efficient architecture for a high-speed cell concentrator/distributor(HCCD) in an ATM(Asynchronous Transfer Mode) switch and by analyzeing the simulation results evaluate the performance of the proposed architecuture. The proposed HCCD distributes cells from a switch link to local processors, or concentrates cells from local processor s to a switch link. This design is to guarntee a high throughput for the IPC (inter-processor communication) link in a distributed ATM switching system. The HCCD is designed in a moudlar architecture to provide the extensibility and the flexibility. The main characteristics of the HCCD are 1) Adaption of a local CPU in HCCD for improving flexibility of the system, 2) A cell-baced statistical multiplexing function for efficient multiplexing, 3) A cell distribution function based on VPI(Virtual Path Identifier), 4) A bypassing capability for IPC between processor attached to the same HCCD, 5) A multicasting capability for point-to-multipoint communication, 6) A VPI table updating function for the efficient management of links, 7) A self-testing function for detecting system fault.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.25-35
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• 1998

The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.407-415
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• 2007

In parallel cluster computing systems, the efficiency of communication between computing nodes is one of important factors that decide overall system performance. Accordingly, many researchers have studied on high-performance inter-node communication. The recently launched multi-core processor, however. increases the importance of intra-node communication as well because the more the number of cores in a node, the more the number of parallel processes running in the same node. Though there have been studies on intra-node communications, these have limited considerations on the state-of-the-art systems. In this paper, we propose a Linux kernel module that minimizes the number of data copy by exploiting the memory mapping mechanism for high-performance intra-node communication. The proposed kernel module supports the Linux kernel version 2.6. The performance measurements over a multi-core system present that the proposed kernel module can achieve lower latency up to 62% and higher throughput up to 144% than an existing kernel module approach. In addition, the measurements reveal that the performance of intra-node communication can vary significantly based on whether the cores that run the communication processes are belong to the same processor package (i.e., sharing the L2 cache).

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.1006-1011
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• 1993

In this study, a DNC(Distributed Numerical Control) management system is designed that can directly control and manage hybrid CNC machine tools on real-time. And management software is developed to inter-communicate field informations with CNC controllers using an interface processor(Intelligent Multi Communication Board, IMCB). Especially, IMCB supports that DNC system sends and receives part program with CNC controllers in the form of real-time multi-tasking.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.303-310
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• 2006

The sorting algorithms have been developed to take advantage of distributed computers. But the speedup of parallel sorting algorithms decrease rapidly with increased number of processors due to parallel processing overhead such as context switching time and inter-processor communication cost. In this paper, we propose a parallel sorting method which provides linear speedup of an optimal serial algorithm for a system with a large number of processors. This algorithm may even provide superlinear speedup for a practical system. The algorithm takes advantage of an interconnection network properties and its protocol.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.65-73
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• 2000

This paper deals with a design and performance analysis of a parallel signal processing system based on TMS320C67x. With an emphasis on the board-level design of the processor unit four models are proposed with different memory configurations and internal bus schemes. Several approaches to parallel processing of 2D FFT are also presented to be used for performance analysis. The performance of four board models are estimated and compared in terms of the time spent for local memory access, inter-processor communication, and inter-board communication. The results of performance analysis show that, when performance and implementation complexity are taken into account, the model with both local and shared memories is the most desirable.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.289-440
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• 1998

This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.76-91
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• 1996

In this paper, we proposed the new medium access control protocol for the virtual token bus netowrk. The network is applied to inter-processor communication network of large capacity digital switching system and digital mobile system with distributed control architecture. in the virtual token bus netowrk, the existing medium access control protocols hav ea switchove rtime overhead when traffic load is light or asymmetric according ot arbitration address of node that has message to send. The proposed protocol optimized average message delay using cyclic bus access chain to exclude switchover time of node that do not have message to send. Therefore it enhanced bus tuilization and average message delay that degrades the performance of real time communication netowrks. It showed that the proposed protocol is more enhacned than virtual token medium access control protocol and virtual token medium access control protocol iwth reservation through performance analysis.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.27-33
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• 2003

This paper proposes the efficient audit method for the distributed connection information in ATM switch. Based on this method, we design the periodic audit function by a system and immediate audit function by a operator's order. We evaluate the performance about the proposed Audit method. At the result of evaluation, We figure out that the load of call control processor is almost independent of a system load regardless of audit function operation. Therefore, we confirm that the proposed audit method nearly have an effect on the load of call control processor. The proposed audit method can reestablish a Mismatched connection information with a little load.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.31-39
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• 1998

In this paper, we have presented a quantitative performance effect of CCP(Call Control Processor) when SAAL(Signalling ATM Adaptation Layer) function is distributed from CCP to SIMs(Subscriber Interface Modules) in an ATM switching system with distributed architecutre. For the performance analysis, SLAM II simulation language is used and subscriber signalling messageand inter-processor communication messages according to Q.2931 based local call processing procedure are taken into consideration in the proposed queuing network model. The results of simulation are compared with in case of processing SAAL function on CCP. It is observed that the processing utilization of CCP reach 24,000 BHCA and 25,700 BHCAwhen SAAL function load amounts to 10% and 20% of the processing time of the total message, respectively. These values shows that the processing utilization of CCP is alleviated about 7% in comparison with 2,000 BHCA in case that SAAL function is carried out on CCP. Consquently, it is shown that we have to consider seriously how to distribute the functions concerning call processing in a large cale ATM switching system architecture accomodating a number of SIMs.