• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.543-551
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• 2017

SOL (Short, Open and Load) calibration based on iterative error sensitivity is proposed in this paper. With advanced SOL calibration, unknown parasitic parameters at on-chip terminations are accurately estimated up to 20 GHz. Artificial terminations are designed on printed circuit board (PCB) to experiment the proposed method. On-chip SHORT, OPEN and LOAD fabricated inside silicon shows the accuracy of proposed calibration method through the comparison with known fixture S-parameter after de-embedding.

• Proceedings of the KIPE Conference
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• 1998.11a
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• pp.5-8
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• 1998

The adaptation to vector control theory is so generalized that it is widely used for implementing the high-performance of AC machine. Nowadays, One-Chip microprocessors or DSP chips are being well-used to implement Vector Control algorithm. DSP Chip have less flexibility for memory decoding and I/O rather than One-Chip microprocessor so that is requires more additional circuit and high cost. And the past One-Chip micro processors have difficult of implementation the complex algorithm because of small memory capacity and low arithmetic performance. Therefore we implemented the vector control algorithm of PMSM(Permanent Magnetic Synchronous Motors) using 80296SA form intel , which have many features as 6M memory space, 500MHz clock frequency, including memory decoding circuit and general I/O, Special I/O(EPA, Interrupt controller, Timer/Count, PWM generator) which is proper controller for the complex algorithm or operation program requiring so much memory capacity, So in this paper we fully digitized the vector control of PMSM included SVPWM Voltage controller using the intel 80296SA

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.41-45
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• 2013

Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a great challenge to the design of a power distribution network (PDN). Power rails merging is a popular option used today in a PDN design as numerous power rails are no longer feasible due to form factor limitation and cost constraint. In this paper, the criteria and limitations for power rails merging are discussed. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.1
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• pp.57-61
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• 1984

This paper deals with the selection of minimal test instruction set for microprocessor data processing test. This test method is based on a function description of the instructions which are obtained from the data given by the user's manual. Selecting procedure is done in 3 steps: 1) a test execution graphs are represented on the instructions which are grouped functionally, 2) the essential graphs, the eliminable graphs, the eliminable graphs, and the eligible graphs are built, 3) optimal test instruction set from the essential graphs and the eligible graphs is defined. In the case of INTEL 8048, 50 test instructions can be selected optimally from 8048 instruction repertories (96 instructions)

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.114-117
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• 2007

DES is an improvement of the algorithm Lucifer developed by IBM in the 1977. IBM, the National Security Agency (NSA) and the National Bureau of Standards (NBS now National Institute of Standards and Technology NIST) developed the DES algorithm. The DES has been extensively studied since its publication and is the most widely used symmetric algorithm in the world. But nowadays, Triple DES (TDES) is more widely used than DES especially in the application in case high level of data security is required. Even though TDES can be implemented based on standard algorithm, very high speed TDES codec performance is required to process when encrypted high resolution satellite image data is down-linked at high speed. In this paper, Intel SSE2 (Streaming SIMD (Single-Instruction Multiple-Data) Extensions 2 of Intel) is applied to TDES Decryption algorithm and proved its effectiveness in the processing time reduction by comparing the time consumed for two cases; original TDES Decryption and TDES Decryption with SSE2

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.1
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• pp.58-64
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• 1989

This paper constructs a stochastic model for computer performance evaluation which has several parameters such as the kinds of instruction mix of benchmark programs, distribution and frequency of instruction mix. It shows, by applying the model to the performance evaluation of the Intel 8086/8088 microprocessor, that this model could be utilited not only for performance evaluation of existing computer systems but also for estimation of nonexisting systems.

• Journal of Information Display
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• v.5 no.4
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• pp.38-44
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• 2004

In this paper, a server and client simulator for the web-based multi-view 3D image communication system is implemented by using the IEEE 1394 digital cameras, Intel Xeon server computer and Microsoft's DirectShow programming library. In the proposed system, two-view image is initially captured by using the IEEE 1394 stereo camera and then, this data is compressed through extraction of its disparity information in the Intel Xeon server computer and transmitted to the client system, in which multi-view images are generated through the intermediate views reconstruction method and finally display on the 3D display monitor. Through some experiments it is found that the proposed system can display 8-view image having a grey level of 8 bits with a frame rate of 15 fps.

• Journal of Information Processing Systems
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• v.8 no.2
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• pp.331-346
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• 2012

Task-based programming is becoming the state-of-the-art method of choice for extracting the desired performance from multi-core chips. It expresses a program in terms of lightweight logical tasks rather than heavyweight threads. Intel Threading Building Blocks (TBB) is a task-based parallel programming paradigm for multi-core processors. The performance gain of this paradigm depends to a great extent on the efficiency of its parallel constructs. The parallel overheads incurred by parallel constructs determine the ability for creating large-scale parallel programs, especially in the case of fine-grain parallelism. This paper presents a study of TBB parallelization overheads. For this purpose, a TBB micro-benchmarks suite called TBBench has been developed. We use TBBench to evaluate the parallelization overheads of TBB on different multi-core machines and different compilers. We report in detail in this paper on the relative overheads and analyze the running results.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.834-837
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• 1993

This paper describes the implementation of an autonomous fuzzy logic controller. The controller is endowed with basic control principles and learning constructs which enable it to autonomously modify its control policy based on system performance. The controller lies dormant when system response is satisfactory but if rapidly initiates adaptation in real time when adverse performance is observed. The autonomous fuzzy controller is implemented on an Intel MCS-51 series micro-controller board using an inexpensive 8-bit Intel 8031 processor. The 11.06 MHz micro-controller operates at a rate exceeding 200 "global" look-up table reinforcements per second. This is important when developing practical on-line adaptive controllers for fast systems. It is also significant because an initial controller look-up table could be incorrect or non-existent. The relatively high learning rate enables the controller to learn to control a system even while it is controlling it.

• Journal of Communications and Networks
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• v.9 no.2
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• pp.141-149
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• 2007

Multiple-input multiple-output (MIMO) transmit pre-coding/beamforming can significantly improve system spectral efficiency. However, several obstacles prevent precoding from wide deployment in early wireless networks: The significant feedback overhead, performance degradation due to feedback delay, and the large storage requirement at the mobile devices. In this paper, we propose a precoding method that addresses these issues. In this approach, only 3 or 6 bits feedback is needed to select a precoding matrix from a codebook. There are fifteen codebooks, each corresponding to a unique combination of antenna configuration (up to 4 antennas) and codebook size. Small codebooks are prestored and large codebooks are efficiently computed from the prestored codebook, modified Hochwald method and Householder reflection. Finally, the feedback delay is compensated by channel prediction. The scheme is validated by simulations and we have observed significant gains comparing to space-time coding and antenna selection. This solution was adopted as a part of the IEEE 802.16e specification in 2005.