• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• 한국소음진동공학회논문집
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• 제18권11호
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• pp.1111-1117
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• 2008

During the dynamic analysis of a system, the Coulomb friction law is emploved to calculate the friction force. Since the static friction coefficient is only employed during the zero relative velocity, it is impractical to employ the coefficient during the dynamic analysis. To calculate the static friction force, therefore, some friction models have been developed. In this study, the integration stability and the accuracy of the models are investigated with some numerical examples. The effect of time step size during the numerical integration is also investigated. The numerical study shows that the friction model employed for most commercial codes is not as good as the one proposed in this study.

• 산업진흥연구
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• 제8권3호
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• pp.61-67
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• 2023

본 연구는 증가하는 이주민과 더불어 이에 대한 사회적 배제는 많은 분야에서 지속되고 있는데 착안하여 이주민들이 한국사회에서 겪는 사회적 배제를 극복하고 사회통합을 이룰 수 있는 방안을 제시하고자 한다. 연구결과는 다음과 같다. 첫째, 이주민 관련 법제도를 제.개정하여야 한다. 이주민의 증가로 각종 법제도적 제정은 물론 관련법의 재정비가 불가피하다. 이주민은 자신들의 문화적 고유성과 가치를 인정받고 보존하며, 정주민들과 동등한 자격과 능력을 부여받을 수 있도록 사회적 배제를 극복하게 해야 한다. 둘째, 이주민의 정치참여가 보장되어야 한다. 현재 극히 일부만 열려 있는 이주민의 정치참여가 보장될 때, 한국사회는 다문화사회로 한걸음 진전한다고 볼 수 있다. 셋째, 정주민과 이주민이 공존해야 한다. 이의 전제로 이주민과 공존할 수 있도록 사회적 배제가 극복될 수 있는 터전을 마련해야 한다. 이주민은 정주민에 비해 사회적 배제가 각 분야에서 진행되고 있는 현실을 공존관계로 발전할 수 있게 해야 한다. 결론적으로 증가하는 이주민들이 한국사회에 정착하기 위해서는 우선적으로 이주민들에게 가해지고 있는 사회적 배제가 극복되어야만 사회통합도 이루어질 수 있다.

• 한국산업융합학회 논문집
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• 제8권2호
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• pp.69-76
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• 2005

This study for Customer Satisfaction(Customer Focus) by Profit security' in the field Process improvement activity and man-power upgrade by DAS(DATA Acquisition System) in the Plant that is fusion Off Line and On Line(IT), Especially the basic of the most foundation in the beginning Step of Toyota system is 3-jeong(a standard instrument; right volume, right box, right position), 5S(Seiri, Seiton, Seisoh, Seiketsu, Sitsuke ; KAISEN, KANBNA System(for Logistic), Further more KPC has established the digital environment such as CIM ; Computer Integrated Manufacturing), IMS ; Intelligent Manufacturing System ERP ; Enterprise Resource Planning, DAS; Data Acquisition System, Autonomous QC & SPC etc,.) in order to realize the intelligent informatization, which is core base for obtaining the competitive power and for responding to the various 21C management environment in flexibility. In this digital management environment, continuously and powerfully they would advance for becoming the best of the world. For strategic changes to take place in industry 3 key important factors need to be included ; Integration of tasks function and process, Decentralization of information, Responsibility, Finally simplification of products and product structures.

• 한국정밀공학회지
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• 제29권5호
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• pp.563-571
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• 2012

In 3D integration package using TSV technology, bonding is the core technology for stacking and interconnecting the chips or wafers. During bonding process, however, warpage and high stress are introduced, and will lead to the misalignment problem between two chips being bonded and failure of the chips. In this paper, a finite element approach is used to predict the warpages and stresses during the bonding process. In particular, in-plane deformation which directly affects the bonding misalignment is closely analyzed. Three types of bonding technology, which are Sn-Ag solder bonding, Cu-Cu direct bonding and SiO2 direct bonding, are compared. Numerical analysis indicates that warpage and stress are accumulated and become larger for each bonding step. In-plane deformation is much larger than out-of-plane deformation during bonding process. Cu-Cu bonding shows the largest warpage, while SiO2 direct bonding shows the smallest warpage. For stress, Sn-Ag solder bonding shows the largest stress, while Cu-Cu bonding shows the smallest. The stress is mainly concentrated at the interface between the via hole and silicon chip or via hole and bonding area. Misalignment induced during Cu-Cu and Sn-Ag solder bonding is equal to or larger than the size of via diameter, therefore should be reduced by lowering bonding temperature and proper selection of package materials.