• 한국전자파학회논문지
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• 제15권3호
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• pp.284-290
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• 2004

본 논문에서는 기판상의 인덕터가 박막공진 여파기의 성능에 미치는 영향을 고찰하기 위하여 두 종류의 사다리형 박막공진 여파기를 설계 및 제작하였다. 여파기를 이루고 있는 박막공진기들의 압전물질은 AIN이고, 전극은 백금(Pt)으로 이루어졌으며 기판에 의한 오버모드(overmode) 현상을 제거하기 위하여 air-gap 형태로 제작되었다. 듀플렉서를 이루고 있는 송신용 여파기의 특성을 보이기 위해 4개의 직렬 공진기와 2개의 병렬 공진기로 이루어진 사다리형 4/2단 여파기가 제작되었으며, 수신용 여파기의 성능을 보이기 위해서는 3/4단으로 제작되었다. 여파기의 성능을 개선하기 위해 사용된 기판상의 인덕터들은 2 ㎓ 대역에서 약 5∼9 정도의 Q값 특성을 보였으며, 인덕터가 연결된 여파기는 연결되지 않은 경우에 비해 약 10∼12 ㏈ 정도의 개선된 대역외 저지특성을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.25-26
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• 2011

In some cases of grid connected system using photovoltaic modules, high voltage step up ratio is required. In this paper, non-isolated 2-stage cascaded boost converter with coupled inductor is proposed. Due to reduce the input current ripple and size of the inductor by using coupled inductor method, this topology is suitable for MIC(Module Integrated Converter). The operational characteristic of the proposed topology is verified through the theorical analysis, simulation and experimental waveform.

• 전기학회논문지
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• 제64권1호
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• pp.143-148
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• 2015

In this paper a new method is proposed for realizing active floating inductors from voltage differencing transconductance amplifier(VDTA) which is being studied nowadays. This proposed method employs only one VDTA and one transconductance for designing an active inductor from a passive floating inductor and implementing it to integrated circuits. The number of CMOS transistors can be considerably reduced from 6~18 as 1~3 gm circuits can be eliminated and even without R the design can be made, which can help in reducing the size of the circuit and power consumption. The proposed VDTA floating inductor was successfully used in constructing 1 MHz second order biquad active bandpass filter and bandwidth could be adjusted from 77kHz~1.59MHz by the changes made in gm from 6uS~20uS.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 I
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• pp.270-273
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• 2003

The design, fabrication, and measured result of a 4.7 GHz differential VCO (Voltage Controlled Oscillator) for a 5.2 GHz WLAN (Wireless Local Area Network) applications is presented. The circuit is designed in a 0.35 mm technology employing three metal layers. The design is based on a fully integrated LC tank using spiral inductors. Measured tuning range is 10% of oscillation frequency with a control voltage from 0 to 3.0 V. Oscillation power of $\square$ 2.3 dBm at 4.63 GHz is measured with 21 mA DC current at 3V supply. The phase noise is $\square$ 104.17 dBc/Hz at 1 MHz offset.

• 반도체디스플레이기술학회지
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• 제2권1호
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• pp.11-14
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• 2003

The high Q(quality factor) suspended spiral inductors were fabricated on the silicon substrate by 3D surface micromachined process. The integration of 2.4GHz VCO has been performed by fabricating suspended spiral inductor of the top of CMOS VCO circuit. The phase noise of VCO integrated MEMS inductor is 93.5 dBc/Hz at 100kHz of offset frequency.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.348-348
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• 2008

In recent, the concept of system-on-package (SOP) for highly integrated multifunctional systems has been paid attention to for the miniaturization and high frequency of electronic devices. In order to realize SOP, co-integration of passive devices, such as capacitors, resistors and inductors, and active devices should be achieved. If ceramic thick films can be grown at room temperature, we expect to be able to overcome many problems in conventional fabrication processes. So, we focused on the aerosol deposition method (ADM) as room temperature fabrication technology. ADM is a novel ceramic coating method based on the Room Temperature Impact Consolidation (RTIC) phenomena. This method has a wide range potential for fabrication of co-integration of passive and active devices. In this paper, I will present the future potential of ADM introducing various ceramic dielectric thick films for the integration of electronic ceramics.

• Journal of Power Electronics
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• 제19권5호
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• pp.1069-1073
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• 2019

In this paper, an alternative non-isolated DC-DC converter with a high voltage boosting capability is proposed. Two inductors are used and one of them has its flux linkage increases during its charging period to achieve a high step-up voltage gain. Among the three integrated capacitors, one portrays the partial characteristic of the switched-capacitor technique, while the other two are connected in series across the load. With the two switches controlled using the same duty cycle, the proposed topology demonstrates the merits of a higher and wider range of step-up voltage gain when compared with recent topologies. In addition, a reduction in loss is induced and a higher efficiency is ensured with all the voltage stresses constrained within the output voltage. Operation of the proposed converter is analyzed and validated through experimental results obtained with a prototype.

• ETRI Journal
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• 제25권2호
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• pp.65-72
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• 2003

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6" Si wafer with a 25${\mu}m$ thick $SiO_2$ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 ${\Omega}$ coplanar transmission line (W=50${\mu}m$, G=20${\mu}m$). Using benzo cyclo butene (BCB) interlayers and a 10 ${\mu}m$ Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30-120, depending on geometrical parameters and inductance values of 0.35-35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high-speed wireless LAN applications. The chip sizes of the wafer-level-packaged RF IPDs and wire-bondable RF IPDs were 1.0-1.5$mm^2$ and 0.8-1.0$mm^2$, respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand-held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.

• Journal of Power Electronics
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• 제17권2호
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• pp.411-421
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• 2017

An approach based on a 2D lumped model is presented to quantify the voltage transfer gain (VTG) in power converter low power planes. The advantage of the modeling approach is the ease with which typical noise reduction devices such as decoupling capacitors or ferrite beads can be integrated into the model. This feature is enforced by a new modular approach based on effective matrix partitioning, which is presented in the paper. This partitioning is used to decouple power plane equations from external device impedance, which avoids the need for rewriting of a whole set of equation at every change. The model is quickly solved in the frequency domain, which is well suited for an automated layout optimization algorithm. Using frequency domain modeling also allows the integration of frequency-dependent devices such inductors and capacitors, which are required for realistic computation results. In order to check the precision of the modeling approach, VTGs for several layout configurations are computed and compared with experimental measurements based on scattering parameters.