• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.4
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• pp.282-285
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• 2019

A 100-nm gate-length metamorphic high electron mobility transistor(mHEMT) with a T-shaped gate was fabricated using a two-step gate recess and characterized for DC and microwave performance. The mHEMT device exhibited DC output characteristics having drain current($I_{dss}$), an extrinsic transconductance($g_m$) of 1,090 mS/mm and a threshold voltage($V_{th}$) of -0.65 V. The $f_T$ and $f_{max}$ obtained for the 100-nm mHEMT device were 190 and 260 GHz, respectively. The developed mHEMT will be applied in fabricating W-band monolithic microwave integrated circuits(MMICs).

• Journal of Space Technology and Applications
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• v.3 no.4
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• pp.333-341
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• 2023

This study aims to develop technology for testing and verifying the space radiation environment of miniature space components using the facilities of the domestic 100 MeV proton accelerator and the Space Component Test Facility at the Space Testing Center. As advancements in space development progress, high-performance satellites increasingly rely on densely integrated circuits, particularly in core components components like memory. The application of semiconductor components in essential devices such as solar panels, optical sensors, and opto-electronics is also on the rise. To apply these technologies in space, it is imperative to undergo space environment testing, with the most critical aspect being the evaluation and testing of space components in high-energy radiation environments. Therefore, the Space Testing Center at the Korea testing laboratory has developed a radiation testing device for memory components and conducted radiation impact assessment tests using it. The investigation was carried out using 100 MeV protons at a low flux level achievable at the Gyeongju Proton Accelerator. Through these tests, single event upsets observed in memory semiconductor components were confirmed.

• The KIPS Transactions:PartC
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• v.18C no.5
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• pp.343-360
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• 2011

The objective of this paper is to analyze and characterize to simulate routing observations on end-to-end routing circuits and a ping experiment of a virtual network after modeling, such as IPv6 migration, an OSPFv3 routing experiment based on an IPv6 environment, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing using IPv6 planning and operations in an OPNET Modeler. IPv6 deployment based largely on the integrated wired and wireless network was one of the research tasks at hand. The previous studies' researchers recommended that future research work be done on the explicit features of both OSPFv3 and EIGRP protocols in the IPv4/IPv6 environment, and more research should be done to explore how to improve the end-to-end IPv6 performance. Also, most related work was performed with an IPv4 environment but lacked studies related to the OSPFv3 virtual network based on an end-to-end IPv6 environment. Hence, this research continues work in previous studies in analyzing IPv6 migration, an OSPFv3 routing experiment based on IPv6, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing. In the not too distant future, before enabling the default IPv6, it would help to understand network design and deployment based on an IPv6 environment through IPv6 planning and operations for the end-user perspective such as success or failure of connection on IPv6 migration, exploration of an OSPFv3 routing circuit based on an end-to-end IPv6 environment, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing. We were able to observe an optimal route for modeling of an end-to-end virtual network through simulation results as well as find what appeared to be a fast ping response time VC server to ensure Internet quality of service better than an HTTP server.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.61-66
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• 2012

Chemical Mechanical Planarization (CMP) is a polishing process used in the microelectronic fabrication industries to achieve a globally planar wafer surface for the manufacturing of integrated circuits. Pad conditioning plays an important role in the CMP process to maintain a material removal rate (MRR) and its uniformity. For metal CMP process, highly acidic slurry containing strong oxidizer is being used. It would affect the conditioner surface which normally made of metal such as Nickel and its alloy. If conditioner surface is corroded, diamonds on the conditioner surface would be fallen out from the surface. Because of this phenomenon, not only life time of conditioners is decreased, but also more scratches are generated. To protect the conditioners from corrosion, thin organic film deposition on the metal surface is suggested without requiring current conditioner manufacturing process. To prepare the anti-corrosion film on metal conditioner surface, vapor SAM (self-assembled monolayer) and FC (Fluorocarbon) -CVD (SRN-504, Sorona, Korea) films were prepared on both nickel and nickel alloy surfaces. Vapor SAM method was used for SAM deposition using both Dodecanethiol (DT) and Perfluoroctyltrichloro silane (FOTS). FC films were prepared in different thickness of 10 nm, 50 nm and 100 nm on conditioner surfaces. Electrochemical analysis such as potentiodynamic polarization and impedance, and contact angle measurements were carried out to evaluate the coating characteristics. Impedance data was analyzed by an electrical equivalent circuit model. The observed contact angle is higher than 90o after thin film deposition, which confirms that the coatings deposited on the surfaces are densely packed. The results of potentiodynamic polarization and the impedance show that modified surfaces have better performance than bare metal surfaces which could be applied to increase the life time and reliability of conditioner during W CMP.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}