• Journal of the Korea Society of Computer and Information
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• v.16 no.9
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• pp.1-10
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• 2011

Unfortunately, in current microprocessors, increasing the frequency causes increased power consumption and reduced reliability whereas it improves the performance. To overcome the power and thermal problems in the singlecore processors, multicore processors has been widely used. For 2D multicore processors, interconnection is regarded as one of the major constraints in performance and power efficiency. To reduce the performance degradation and the power consumption in 2D multicore processors, 3D integrated design technique has been studied by many researchers. Compared to 2D multicore processors, 3D multicore processors get the benefits of performance improvement and reduced power consumption by reducing the wire length significantly. However, 3D multicore processors have serious thermal problems due to high power density, resulting in reliability degradation. Detailed thermal analysis for multicore processors can be useful in designing thermal-aware processors. In this paper, we analyze the impact of workload distribution, distance to the heat sink, and number of stacked dies on the processor temperature. We also analyze the effects of the temperature on overall system performance. Especially, this paper presents the guideline for thermal-aware multicore processor design by analyzing the thermal problems in 2D multicore processors and 3D multicore processors.

• Journal of Engineering Education Research
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• v.10 no.3
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• pp.79-92
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• 2007

To enhance the excellence, effectiveness and economical efficiency in the learning process, we implement a hybrid educational system for engineering experiments where web-based virtual laboratory systems and distance education systems are properly integrated. In the first stage, we designed client/server distributed environment and developed web-based virtual laboratory systems for digital systems and electrical/electronic circuit experiments. The proposed virtual laboratory systems are composed of four important sessions and their management system: concept learning session, virtual experiment session, assessment session. With the aid of the management system every session is organically tied up together to achieve maximum learning efficiency. In the second stage, we have implemented efficient and cost-effective distant laboratory systems for practicing electric/electronic circuits, which can be used to eliminate the lack of reality occurred during virtual laboratory session. The use of simple and user-friendly design allows a large number of people to access our distant laboratory systems easily. Thus, self-guided advanced training is available even if a lot of expensive equipment will not be provided in the on-campus laboratories. The proposed virtual/distant laboratory systems can be used in stand-alone fashion, but to enhance learning efficiency we integrated them and developed a hybrid educational system for engineering experiments. Our hybrid education system provides the learners with interactive learning environment and a new approach for the delivery of engineering experiments.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.11
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• pp.63-70
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• 2001

We demonstrate the MMIC (monolithic microwave integrated circuit) frequency doublers generating stable and low-cost 29 GHz local oscillator signals from 14.5 GHz input signals. These devices were designed and fabricated by using the M MIC integration process of $0.1\;{\mu}m$ gate-length PHEMTs (pseudomorphic high electron mobility transistors) and passive components. The measurements showed S11 or -9.2 dB at 145 GHz, S22 of -18.6 dG at 29 GHz and a minimum conversion loss of 18.2 dB at 14.5 GHz with an input power or 6 dBm. Fundamental signal of 14.5 GHz were suppressed below 15.2 dBe compared to the second harmonic signal at the output port, and the isolation characteristics of fundamental signal between the input and the output port were maintained above :i0 dB in the frequency range 10.5 GHz to 18.5 GHz. The chip size of the fabricated MMIC frequency doubler is $1.5{\times}2.2\;mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.844-853
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• 2008

This paper describes the design of a FEM(Front End Module) having power detection function for mobile handset application. The designed FEM consists of a MMIC(Monolithic Microwave Integrated Circuits) power amplifier chip, SAW Tx filter and duplexer, diode power detector and stripline matching circuit. An LTCC(Low Temperature Co-fired Ceramics) technology is adopted for miniaturized FEM. The frequency band is $824{\sim}869$ MHz which is the uplink Tx band of the CDMA mobile system. The size of designed FEM is $7.0{\times}5.5{\times}1.5\;mm^3$, which is an ultra-small size even though the power detector circuit is included. All sub-components of FEM have been developed and measured in advance before being integrated into FEM. The measured output power and gain are 27 dBm and 27 dB, respectively. In addition, the measured ACPR characteristics are 46.59 dBc and 55.5 dBc at 885 kHz and 1.98 MHz offset, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.105-111
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• 2007

In this paper, we designed and fabricated a 3-dB tandem coupler using air-bridge technology for millimeter-wane monolithic integrated circuits, operating at W-band($75{\sim}110\;GHz$) frequency. Tightly edge-coupled CPW line has low directivity due to different even-mode and odd-mode phase velocity. To overcome this disadvantage, a 3-dB tandem coupler which comprises the two-sectional weakly parallel-coupled lines with equal phase velocity was designed at W-band. The proposed coupler was fabricated using air-bridge technology to monolithically materialize the uniplanar coupler structure instead of conventional multilayer or wire bonded structure. From the measurements, the coupling coefficient of $2.9{\sim}3.6\;dB$ and the good phase difference of $91.2{\pm}2.9^{\circ}$ were obtained in broad frequency range of $75{\sim}100\;GHz$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.613-623
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• 2012

In this paper, we present an ultra miniaturized voltage tuned oscillator, with HMIC-type amplifier and phase shifter, using LTCC artificial dielectric resonator. ADR which consists of periodic conductor patterns and stacked layers has a smaller size than a dielectric resonator. The design specification of ADR is obtained from the design goal of oscillator. The structure of the ADR with a stacked circular disk type is chosen. The resonance characteristic, physical dimension and stack number are analyzed. For miniaturization of ADRO, the ADR is internally implemented at the upper part of the LTCC substrate and the other circuits, which are amplifier and phase shifter are integrated at the bottom side respectively. The fabricated ADRO has ultra small size of $13{\times}13{\times}3mm^3$ and is a SMT type. The designed ADRO satisfies the open-loop oscillation condition at the design frequency. As a results, the oscillation frequency range is 2.025~2.108 GHz at a tuning voltage of 0~5 V. The phase noise is $-109{\pm}4$ dBc/Hz at 100 kHz offset frequency and the power is $6.8{\pm}0.2$ dBm. The power frequency tuning normalized figure of merit is -30.88 dB.

• The KIPS Transactions:PartA
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• v.19A no.1
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• pp.51-60
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• 2012

IC(Integrated circuits)card, generally be named smard card, embedded MPU(Micro Processor Unit) of small-size, memory, EEPROM, Card Operating System(COS) and security algorithm. The IC card is used in almost all industry such as a finance(credit, bank, stock etc.), a traffic, a communication, a medical, a electronic passport, a membership management and etc. Recently, a application field of IC card is on the increase by method for payments of T-commerce, as T-commerce is becoming a new growth engine of the broadcating industry by trend of broadcasting and telecommunication convergence, smart mechanization of TV. For example, we can pay in IC credit card(or IC cash card) on T-Commerce. or we can be provided TV banking service in IC cash card such as ATM. However, so far, T-commerce payment services have weakness in security such as storage and disclosure of card information as well as dropping sharply about custom ease because of taking advantage of card information input method using remote control. To solve this problem, This paper developed processing payment module for implementing TV electronic payment system using IC credit card payment standard, EMV.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.180-180
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• 2012

Heteroepitaxial GaN nano- and micro-rods (NMRs) are one of the most promising structures for high performance optoelectronic devices such as light emitting diodes, lasers, solar cells integrated with Si-based electric circuits due to their low dislocation density and high surface to volume ratio. However, heteroepitaxial GaN NMRs growth using a metal-organic vapor phase epitaxy (MOVPE) machine is not easy due to their long surface diffusion length at high growth temperature of MOVPE above $1000^{\circ}C$. Recently some research groups reported the fabrication of the heteroepitaxial GaN NMRs by using MOVPE with vapor-liquid-solid (VLS) technique assisted by metal catalyst. However, in the case of the VLS technique, metal catalysts may act as impurities, and the GaN NMRs produced in this mathod have poor directionallity. We have successfully grown the vertically well aligned GaN NMRs on Si (111) substrate by means of self-catalystic growth methods with pulsed-flow injection of precursors. To grow the GaN NMRs with high aspect ratio, we veried the growth conditions such as the growth temperature, reactor pressure, and V/III molar ratio. We confirmed that the surface morphology of GaN was strongly influenced by the surface diffusion of Ga and N adatoms related to the surrounding environment during growth, and we carried out theoretical studies about the relation between the reactor pressure and the growth rate of GaN NMRs. From these results, we successfully explained the growth mechanism of catalyst-free and mask-free heteroepitaxial GaN NMRs on Si (111) substrates. Detailed experimental results will be discussed.