• 한국정보처리학회논문지
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• 제4권8호
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• pp.2152-2162
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• 1997

본 논문은 파이프라인 방식의 ASIC 데이타 경로를 제어하기 위한 시간 정지형 콘트롤러의 자동합성에 관한 연구이다. 콘트롤 합성은 콘트롤 사양의 자동 생성과 유한상태기의 합성 및 최적화 단계로 구성된다. 이 유한상태기는 수평분할 방식을 응용하여 최적화되며 최소 면적의 콘트롤러가 합성된다. 실험을 통해 제안된 방식으로 생성된 콘트롤러와 기존 방식으로 합성된 유한상태기 콘트롤러를 비교하였는데 콘트롤러의 면적에서 있어서 큰 감소를 보여준다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.126-128
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• 2007

This paper presents a new soft switching dc-to-dc converter that employs IM transformer. Detailed analysis and design considerations of the proposed circuits are presented. By applying the proposed magnetic integration procedure, new integrated magnetic circuits featuring low loss, simple structure are then developed to overcome the limitations of prior art. Consequently, the power loss and the size of the integrated magnetic device are greatly reduced. The operation and performance of the proposed converter are demonstrated with an experimental converter that delivers a 5V/5A output from a 48V input at the maximum efficiency of 90 %.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.137-140
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• 2002

The algorithm for calculating the base-collector breakdown voltage of NPN BJT(Bipolar Junction Transistor) for integrated circuits is proposed. The method for calculating the electric field using the solution of Poisson's equation is presented and the method for calculating the breakdown voltage using the integration of ionization coefficients is presented. The base-collector breakdown voltage of NPN BJT using 20V process obtained from the proposed method shows an averaged relative error of 8.0% compared with the measured data.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.141-144
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• 2002

The method of the analysis of the base Gummel number of the PNP BJT(Bipolar Junction Transistor) for integrated circuits based upon the semiconductor physics is proposed and the method of calculating the doping profile of the base region using process conditions is presented. The transistor saturation current obtained from the proposed method of PNP BJT using 20V and 30V process shows an averaged relative error of 6.7% compared with the measured data.

• Journal of Multimedia Information System
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• 제8권2호
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• pp.143-146
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• 2021

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.81-84
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• 2004

Required characteristics of poly-Si TFT's are investigated for the implementation of analog circuits to be integrated on System-on-Glass (SoG). Matching requirements on resistor values, threshold voltage and mobility of poly-Si TFT's are derived as a function of the resolution of display system. Effective mobility of poly-Si TFT's required for the realization of source driver is analyzed for various panel sizes.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.319-322
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• 1998

A 20 GHz 2-stage MMIC (Monolithic Microwave Integrated Circuits) LNA(Low Noise Amplifiers) has been designed. The pHEMT with gate length of 1.15 um has been used to provide ultra low noise and high gain amplification. Series and Shunt feedback circuits were interted to ensured high stability over frequency range of DC to 60 GHz. The size of designed MMIC LNA is 2285um x 2000um(4.57mm2). The simulated noise figure of MMIC LNA is less than 1.7 dB over frequency range of 20 GHz to 21 GHz.

• 전기의세계
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• 제23권3호
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• pp.70-76
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• 1974

Computer is used to analyze nonlinear networks. Integrated circuits and new nonlinear elements have generated much interest in nonlinear circuit theory. A key to the understanding and analysis of nonlinear circuits is the study of characteristics for nonlinear elements and nonlinear resistive networks both in theory and in computation. In this apper, an iteration method using cut set analysis for nonlinear dc analysis based on Branin's method is described. Application of this algorithm to solve two nonlinear problems, is presented and a possible method of improving the basic algorithm by means of a sparse matrix technique is described.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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• pp.5-8
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• 2001

In this paper, we have space vector PWM(Pulse Width Modulation) circuits on the FPGA(Field Programmable Gate Arry) chip designed by VHDL(Very high speed integrated circuit Hardware Description Language). This circuit parts was required at controlling the AC servo motor system and should have been designed with many discrete digital logics. In the result of this study, peripheral circuits are to be simple and the designed logic terms are robust and precise. Because of it's easy verification and implementation, we could deduced that the customize FPGA chip show better performance than that of circuit modules parts constituted of discrete IC.

• ETRI Journal
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• 제37권6호
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• pp.1154-1164
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• 2015

This paper proposes a fully sensorless driver for a permanent magnet synchronous motor (PMSM) integrated with a digital motor controller and an analog pre-driver, including sensing circuits and estimators. In the motor controller, a position estimator estimates the back electromotive force and rotor position using a sliding-mode observer. In the pre-driver, drivers for the power devices are designed with a level shifter and isolation technique. In addition, a current sensing circuit measures a three-phase current. All of these circuits are integrated in a single chip such that the driver achieves control of the speed with high accuracy. Using an IC fabricated using a $0.18{\mu}m$ BCDMOS process, the performance was verified experimentally. The driver showed stable operation in spite of the variation in speed and load, a similar efficiency near 1% compared to a commercial driver, a low speed error of about 0.1%, and therefore good performance for the PMSM drive.