• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.2
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• pp.123-133
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• 2012

This paper discuss about DNA watermarking using coding DNA sequence (CDS) for the authentication, the privacy protection, or the prevention of illegal copy and mutation of DNA sequence and propose a DNA watermarking scheme with the mutation robustness and the animo acid preservation. The proposed scheme selects a number of codons at the regular singularity in coding regions for the embedding target and embeds the watermark for watermarked codons and original codons to be transcribed to the same amino acids. DNA base sequence is the string of 4 characters, {A,G,C,T} ({A,G,C,U} in RNA). We design the codon coding table suitable to watermarking signal processing and transform the codon sequence to integer numerical sequence by this table and re-transform this sequence to floating numerical sequence of circular angle. A codon consists of a consecutive of three bases and 64 codons are transcribed to one from 20 amino acids. We substitute the angle of selected codon to one among the angle range with the same animo acid, which is determined by the watermark bit and the angle difference of adjacent codons. From in silico experiment by using HEXA and ANG sequences, we verified that the proposed scheme is more robust to silent and missense mutations than the conventional scheme and preserve the amino acids of the watermarked codons.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.211-216
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• 2012

Control Theory for continuous-time system has been well developed. Due to the development of computer technology, digital control scheme are employed in many areas. When delays are in control systems, it is hard to control the system efficiently. Delays by controller-to-actuator and sensor-to-controller deteriorate control performance and could possibly destabilize the overall system. In this paper, a new approximated discretization method and digital design for control systems with multiple state, input and output delays and a generalized bilinear transformation method with a tunable parameter are also provided, which can re-transform the integer time-delayed discrete-time model to its continuous-time model. Illustrative example is given to demonstrate the effectiveness of the developed method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.18-27
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• 2012

Optimal quantizers in conducting the entropy-constrained quantization for high bit rates have the lattice structure. The quantization process is simple due to the regular structure and various quantization algorithms are proposed depending on the lattice. In this paper, such a lattice vector quantization is implemented by using the sample-adaptive product quantizer (SAPQ). It is shown that several important lattices can be implemented by SAPQ and the lattice vector quantization can be performed by using a simple integer-transform function of scalar values within SAPQ. The performance of the proposed lattice SAPQ is compared to the entropy-constrained scalar quantizer and the entropy-constrained SAPQ (ECSAPQ) at a similar encoding complexity. Even though ECSAPQ shows a good performance at low bit-rates, lattice SAPQ shows better performance than the ECSAPQ case for a wide range of bit rates.

• The Journal of Information Technology
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• v.5 no.4
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• pp.129-137
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• 2002

In this paper, a public key knapsack cryptosystem algorithm is based on the security to a difficulty of polynomial factorization in computer communication networks is proposed. For the proposed public key knapsack cryptosystem, a polynomial vector Q(x,y,z) is formed by transform of superincreasing vector P, a polynomial g(x,y,z) is selected. Next then, the two polynomials Q(x,y,z) and g(x,y,z) is decided on the public key. The enciphering first selects plaintext vector. Then the ciphertext R(x,y,z) is computed using the public key polynomials and a random integer $\alpha$. For the deciphering of ciphertext R(x,y,z), the plaintext is determined using the roots x, y, z of a polynomial g(x,y,z)=0 and the increasing property of secrety key vector. Therefore a public key knapsack cryptosystem is based on the security to a difficulty of factorization of a polynomial g(x,y,z)=0 with three variables. The propriety of the proposed public key cryptosystem algorithm is verified with the computer simulation.

• The Journal of Information Technology
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• v.5 no.4
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• pp.1-8
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• 2002

This thesis is about power line communication(PLC) over the low voltage grid. The main advantage with power line communication is the use of an existing infrastructure. The PLC channel can be modeled as having multi-path propagation with frequency-selective fading, typical power lines exhibit signal attenuation increasing with length and frequency. OFDM(Orthogonal Frequency Division Multiplexing) is a modulation technique where multiple low data rate carriers are combined by a transmitter to form a composite high data rate transmission. To implement the multiple carrier scheme using a bank of parallel modulators would not be very efficient in analog hardware. Each carrier in an OFDM is a sinusoid with a frequency that is an integer multiple of a base or fundamental sinusoid frequency. Therefore, each carrier is a like a Fourier series component of the composite signal. In fact, it will be shown later that an OFDM signal is created in the frequency domain, and then transformed into the time domain via the Discrete Fourier Transform(DFT).

• The Journal of Information Technology
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• v.6 no.2
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• pp.1-8
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• 2003

This paper is about power line communication(PLC) over the low power voltage grid. The main advantage with power line communication is the use of an existing infrastructure. The PLC channel can be modeled as having multi-path propagation with frequency-selective fading, typical power lines exhibit signal attenuation increasing with length and frequency. OFDM(Orthogonal Frequency Division Multiplexing) is a modulation technique where multiple low data rate carriers are combined by a transmitter to form a composite high data rate transmission. To implement the multiple carrier scheme using a bank of parallel modulators would not be very efficient in analog hardware. Each carrier in an OFDM is a sinusoid with a frequency that is an integer multiple of a base or fundamental sinusoid frequency. Therefore, each carrier is a like a Fourier series component of the composite signal. In fact, it will be shown later that an OFDM signal is created in the frequency domain, and then transformed into the time domain via the Discrete Fourier Transform(DFT).

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.392-400
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• 2005

Highly integrated MPEG-4@SP video compression engine, VideoCore, is proposed for mobile application. The primary components of video compression require the high memory bandwidth since they access the external memory frequently. They include motion estimation, motion compensation, quantization, discrete cosine transform, variable length coding, and so on. The motion estimation processor adopted in VideoCore utilizes the small-size local memories such that the video compression system accesses external memory as less frequently as possible. The entire video compression system is divided into two distinct sub-systems: the integer-unit motion estimation part and the others, and both operate concurrently in a pipelined architecture. Thus the VideoCore enables the real-time high-quality video compression with a relatively low operation frequency.

• Journal of Broadcast Engineering
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• v.12 no.4
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• pp.360-372
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• 2007

We propose a fast inter-layer mode decision method by utilizing coding information of base layer upward its enhancement layer inscalable video coding (SVC), also called MPEG-4 part 10 Advanced Video Coding Amendment 3 or H.264 Scalable Extension (SE) which is being standardized. In this paper, when the motion vectors from the base layer have zero motion (0, 0) in inter-layer motion prediction or the Integer Transform coefficients of the residual between current MB and the motion compensated MB by the predicted motion vectors from the base layer are all zero, the block mode of the corresponding block to be encoded at the enhancement layer is determined to be the $16{\times}16$ mode. In addition, if the predicted mode of the MB to be encoded at the enhancement layer is not equal to the $16{\times}16$ mode, then the rate-distortion optimization is only performed on the reduced candidated modes which are same or smaller partitioned modes. Our proposed method exhibits the complexity reduction in encoding time up to 72%. Nevertheless, it shows negligible PSNR degradation and bit rate increase up to 0.25dB and 1.73%, respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.153-164
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• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.