• Title/Summary/Keyword: Insulating layers

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Magnetic Properties of Ni/BN/Co Trilayer Structure: A First Principles Study

  • Hashmi, Arqum;Hong, Jisang
    • Journal of Magnetics
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    • v.20 no.3
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    • pp.201-206
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    • 2015
  • Using the Vienna ab initio simulation package (VASP) incorporating both semiempirical and nonlocal van der Waals interaction, the structural, adsorption, and magnetic properties of Ni/BN/Co systems were investigated. We proposed that the relative spin direction of Ni and Co magnets can be easily tuned, because the total energy difference between ferromagnetic (FM) and antiferromagnetic (AFM) states is small. Despite this feature, very interestingly, both Ni and Co layers manifest half-metallic state, whereas the spacer BN layer becomes weak metal for one monolayer (ML) thickness and an insulating barrier for two ML thicknesses. The half-metallic behavior of the magnetic layers seems very robust, because it is independent of the magnetic coupling between Ni and Co. This finding indicates that the Ni/BN/Co system can be used as a potential candidate for tunneling magnetoresistance system.

A Study on Fabrication of Piezorresistive Pressure Sensor (벌크 마이크로 머쉬닝에 의한 다결정 실리콘 압력센서 제작 관한 연구)

  • 임재홍;박용욱;윤석진;정형진;윤영수
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.677-680
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    • 1999
  • Rapid developing automation technology enhances the need of sensors. Among many materials, silicon has the advantages of electrical and mechanical property, Single-crystalline silicon has different piezoresistivity on 야fferent directions and a current leakage at elevated temperature, but poly-crystalline silicon has the possibility of controling resistivity using dopping ions, and operation at high temperature, which is grown on insulating layers. Each wafer has slightly different thicknesses that make difficult to obtain the precisely same thickness of a diaphragm. This paper deals with the fabrication process to make poly-crystalline silicon based pressure sensors which includes diaphragm thickness and wet-etching techniques for each layer. Diaphragms of the same thickness can be fabricated consisting of deposited layers by silicon bulk etching. HF etches silicon nitride, HNO$_3$+HF does poly -crystalline silicon at room temperature very fast. Whereas ethylenediamice based etchant is used to etch silicon at 11$0^{\circ}C$ slowly.

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Magnetic Properties of Activated Quartz Nanocomposite

  • N.N., Mofa;T.A., Ketegenov;Z.A., Mansurov;Soh, Hyun-Jun;Soh, Dea-Wha
    • Journal of the Speleological Society of Korea
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    • no.78
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    • pp.9-15
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    • 2007
  • The materials showing high structure dispersion with functional properties were developed on the quartz base and those were obtained by mechano-chemical reaction technology. Depending on the processing conditions and subsequent applications the materials produced by mechano-chemical reaction show concurrently magnetic, dielectric and electrical properties. The obtained magnetic-electrical powders classified by aggregate complex of their features as segnetomagnetics, containing a dielectric material as a carrying nucleus, particularly the quartz on that surface one or more layers of different compounds were synthesized having thickness up to 1050nm showing magnetic, electrical properties and others. The similarity of the structure of surface layers of quartz particles subjected to mechano-chemical processing and nano-structure cluspol (clusters in a polymer matrics) material was alsoconfirmed by the fact that the characteristics of ferromagnetic quartz of insulating nano-composite powder were changed with time, after its preparing process was completed.

Formation of Metal Electrode on Si3N4 Substrate by Electrochemical Technique (전기화학 공정을 이용한 질화규소 기판 상의 금속 전극 형성에 관한 연구)

  • Shin, Sung-Chul;Kim, Ji-Won;Kwon, Se-Hun;Lim, Jae-Hong
    • Journal of the Korean institute of surface engineering
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    • v.49 no.6
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    • pp.530-538
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    • 2016
  • There is a close relationship between the performance and the heat generation of the electronic device. Heat generation causes a significant degradation of the durability and/or efficiency of the device. It is necessary to have an effective method to release the generated heat. Based on demands of the printed circuit board (PCB) manufacturing, it is necessary to develop a robust and reliable plating technique for substrates with high thermal conductivity, such as alumina ($Al_2O_3$), aluminium nitride (AlN), and silicon nitride ($Si_3N_4$). In this study, the plating of metal layers on an insulating silicon nitride ($Si_3N_4$) ceramic substrate was developed. We formed a Pd-$TiO_2$ adhesion layer and used APTES(3-Aminopropyltriethoxysilane) to form OH groups on the surface and adhere the metal layer on the insulating $Si_3N_4$ substrate. We used an electroless Ni plating without sensitization/activation process, as Pd particles were nucleated on the $TiO_2$ layer. The electrical resistivity of Ni and Cu layers is $7.27{\times}10^{-5}$ and $1.32{\times}10^{-6}ohm-cm$ by 4 point prober, respectively. The adhesion strength is 2.506 N by scratch test.

Zero-Crack Construction on the Fundamental Mass Concrete Using Double Bubble Sheets and Applying Low Heat Mixture (저발열 배합 및 이중버블시트에 의한 기초 매트 매스 콘크리트의 무균열 시공)

  • Park, Yong-Kyu;Song, Sung-Bin;Baek, Byung-Hoon;Han, Cheon-Goo
    • Proceedings of the Korean Institute of Building Construction Conference
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    • 2006.11a
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    • pp.5-8
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    • 2006
  • This study investigates the field application, Songdo the # 1st WORLD, on zero-crack construction of the fundamental mass concrete using double bubble sheets and applying low heat mixture. Experimental results of hydration heat analysis showed that crack modulus of concrete incorporating 20% of blast furnace slag cement was 1.0 in 120 hours, representing 50% probability of crack occurrence, thus requiring additional measures. As for a curing method, a specimen insulating two layers of vinyl chloride+double bubble sheets exhibited only $16.5^{\circ}C$ difference between upper and lower sections, and it also showed favorable workability as well as competitive economic side. Therefore it was determined to use it for curing method in this field. For the curing results of practical field, using 2 layers of vinyl chloride+double bubble sheets and applying low heat mixture on the fundamental mass concrete in 3A residential building exhibited less than only $15^{\circ}C$ difference between surface and center section of that in 5 days elapse and less than $20^{\circ}C$ in 9 days. This means that the crack by hydration heat was prevented, and other fields structures also resisted the plastic shrinkage by insulating the vinyl, sinking crack by second temping, even drying shrinkage by the mixture of low unit water. Therefore the crack on the placement has not been found so far, since the construction was started before 6 month.

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Study on Resistance Increasement Tendency and Recovery Characteristics of YBCO Thin-film Wire Using Insulation Layer (절연 층이 고려된 YBCO 박막형 선재의 저항 증가 경향 및 회복 특성에 관한 연구)

  • Du, Ho-Ik;Kim, Yong-Jin;Lee, Dong-Hyeok;Han, Byoung-Sung;Song, Sang-Seob;Lee, Jeong-Su;Han, Sang-Chul;Lee, Jung-Phil
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.190-190
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    • 2010
  • The resistance and recovery properties of the YBCO thin-film wire according to the existence and thickness of an insulting layer, and the kinds of stabilization layers, were analyzed at 90 K, 180 K and 250 K. In this study, YBCO thin-film wires with different stabilizing layers and with insulating layers were examined in terms of their various characteristics, such as quenching occurrence, spread, and distribution, based on their resistance increase trends and their recovery from quenching, and the results were qualitatively explained. The results of this study on the characteristics of YBCO thin-film wires' superconducting and normal-conducting phase changes are expected to be useful in designing superconducting power machines and in improving their performance.

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Capacitive-Voltage properties of$(Sr{\cdot}Ca)TiO_{3}$ Ceramics ($(Sr{\cdot}Ca)TiO_{3}$ 세라믹스의 용량-전압 특성)

  • Kang, Jae-Hun;Choi, Woon-Shik;Kim, Chung-Hyeok;Kim, Jin-Sa;Park, Yong-Pill;Song, Min-Jong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11b
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    • pp.34-37
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    • 2001
  • In this study, the capacitance-voltage properties of $(Sr_{1-x}\cdot Ca_x)TiO_3(0.05{\leq}x{\leq}0.20)$-based grain boundary layer ceramics were investigated. The ceramics were fabricated by the conventional mixed oxide method. The sintering temperature and time were $1480\sim1500^{\circ}C$ and 4 hours. respectively. The 2nd phase formed by the thermal diffusion of CuO from the surface leads to very excellent dielectric properties, that is, ${\varepsilon}_r$ >50000, tan$\delta$ <0.05, ${\Delta}C$ < ${\pm}10%.$ The capacitance is almost unchanged below about 20[V] but it decreases slowly about 20[V]. The results of the capacitance-voltage properties indicated that the grain boundary was composed of the continuous insulating layers.

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ELECTRICAL CHARACTERISTICS OF PENTACENE THIN FILM TRANSISTORS WITH STACKED AND SURFACE-TREATED GATE INSULATORS (러빙 처리된 표면의 적층 절연막을 가지는 Pentacene TFT의 전기적 특성)

  • Kang, Chang-Heon;Lee, Jong-Hyuk;Park, Jae-Hoon;Choi, Jong-Sun
    • Proceedings of the KIEE Conference
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    • 2002.07c
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    • pp.1546-1548
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    • 2002
  • In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

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Tunneling Magnetoresistance in Si/$SiO_2$/NiFe/$Al_2$$O_3$/Co Thin Films (Si/$SiO_2$/NiFe/$Al_2$$O_3$/Co 박막의 투과자기저항 특성 연구)

  • 현준원;백주열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.11
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    • pp.934-940
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    • 2001
  • Magnetic properties were investigated for Si/SiO$_2$/NiFe(300 )/A1$_2$O$_3$(t)/Co(200 ) junction related with the parameters of $Al_2$O$_3$. Insulating $Al_2$O$_3$ layer was formed by depositing a 5~40 thick Al layer, followed by a 90~120s RF plasma oxidation in an $O_2$ atmosphere. Magnetoresistance was not observed for tunnel junction with 5~10 thick Al layer, but magnetoresistance was observed large for tunnel junction with 15~40 thick Al layer. Oxidation time did not largely influence magnetoresistance. Tunnel magnetoresistance effect depended on magnetization behavior of two ferromagnetic layers. Tunneling junction was confirmed through nonlinear I-V curve. In this work, tunneling magnetoresistance(TMR) up to 30 % was observed. This apparent TMR is an artifact of the nonuniform current flow over the junction in the cross geometry of the electrodes.

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Characteristics of Semiconductor-Atomic Superlattice for SOI Applications (SOI 응용을 위한 반도체-원자 초격자 구조의 특성)

  • Seo, Yong-Jin;Park, Sung-Woo;Lee, Kyoung-Jin;Kim, Gi-Uk;Park, Chang-Jun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.180-183
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    • 2003
  • The monolayer of oxygen atoms sandwitched between the adjacent nanocrystalline silicon layers was formed by ultra high vacuum-chemical vapor deposition (UHV-CVD). This multi-layer Si-O structure forms a new type of superlattice, semiconductor-atomic superattice (SAS). According to the experimental results, high-resolution cross-sectional transmission electron microscopy (HRTEM) shows epitaxial system. Also, the current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the system may form an epitaxially grown insulating layer as possible replacement of silicon-on-insulator (SOI), a scheme investigated as future generation of high efficient and high density CMOS on SOI.

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