• Journal of Elementary Mathematics Education in Korea
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• v.9 no.1
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• pp.1-18
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• 2005

The purpose of this study is to plan and apply the problem posing program to each unit of elementary mathematics 5-Ga stage, and to make an analysis of their effects on mathematics learning achievements, attitude and interesting. In order to achieve these purposes, the following research problems were set up for the present study: First, we design problem posing program which can be applied to the actual instruction with analyzing the curriculum of mathematics on 5-Ga stage in the seventh national curriculum. Second, we analyze the effect of applying problem posing program on students' mathematics learning achievements. Third, we analyze the effect of applying problem posing program on students' mathematical attitude and interest. The results of this study are as follows: First, the problem posing program developed in this study was more affirmative effects for improving the students' mathematics learning achievements. Second, the problem posing program also had affirmative effects on students' attitude and interest on mathematics. Third, after applying the problem posing program turned out to have a statistical significant correlation between mathematics learning achievements and attitude, and mathematics learning achievements and interest.

• Spatial Information Research
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• v.18 no.4
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• pp.75-88
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• 2010

Recent development in wireless communication and mobile positioning technologies make geosensor networks widely used in the various fields of real world. As a result, much research has been done on the middleware that uses limited energy resources efficiently. However, because traditional middleware does not consider the characteristics of sensor node, such as computing power and specification, the existing middleware call not support the sensor nodes with only the restricted system resource. Therefore, in this paper, we design and implement a new Bytecode based Data Service Middleware supporting energy efficiency in geosensor networks. At first, the proposed middleware provides the optimized functions for sensor nodes by using minimum by tee ode instruction set and data manager supporting hardware abstraction. Secondly, the proposed middleware increases the energy efficiency of sensor node through both data aggregation query processing and data filtering that minimize data transmission by eliminating unnecessary data. Finally, we show from our performance analysis that the proposed middleware is more energy efficient than the existing SwissQM.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• Journal of KIISE:Software and Applications
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• v.32 no.5
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• pp.438-448
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• 2005

This paper proposes an adaptive tutoring system that provides learning materials dynamically according to the learners' teaming character and ability. Our system, in which a learning phase and a test phase are linked together, supports the personalized instruction-learning by providing the teaming materials by level in the learning phase according to the teaming ability estimated in the test phase. We design and implement a tutoring system consisted of an evaluation component and a learning component. An evaluation component uses a computerized adaptive test(CAT) based on item response theory to evaluate learners' ability while a learning component employs fuzzy level set theory so that teaming contents are provided to learners according to learners' level.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.135-141
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• 2020

Today, CPUs in general-purpose computers such as servers, desktops and laptops, as well as home appliances and embedded systems, consist mostly of multicore processors. In order to improve performance, it is required to use an out-of-order execution processor by Tomasulo algorithm as each core processor. An out-of-order execution processor with Tomasulo algorithm can execute the available instructions in any order and perform speculation in order to reduce control dependencies. Therefore, the performance of an out-of-order execution processor can be significantly improved compared to an in-order execution processor. In this paper, an out-of-order execution processor using Tomasulo algorithm and ARM instruction set is designed using VHDL record data types and simulated by GHDL. As a result, it is possible to successfully perform operations on programs written in ARM instructions.

• Journal of The Korean Association For Science Education
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• v.16 no.4
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• pp.429-440
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• 1996

This study examined the effects of the ARCS model for science education and found a way of improving ARCS while finding any weaknesses. More specific research questions were as follows: 1) Does the ARCS model enhance the learners' achivement in highschool Earth Science significantly?; 2) Does the ARCS model enhance the learners' motivation in highschool Earth Science significantly?; 3) What are the weaknesses of the prescriptions of the ARCS model for designing a lesson, if any?; 4) How can the weaknesses of the prescriptions of the ARCS modeI be overcome? In order to fulfill the purpose of this study, the two major research methodologies were implemented: pretest-posttest control group design and formarive research. This study was conducted in two distinct phases: 1) designing a set of instructions for 4 weeks with the principles of the ARCS model (to find the weaknesses of the ARCS model) and 2) teaching the instructions and checking the effectiveness of the ARCS model by pretest and posttest with control and experimental groups(to find weaknesses of the underlying theory of the ARCS). After the experiment, each group took an achievement test and an attitude test on the given instruction and gathered data were analyzed with t-tests. Also, from each four classes 7$\sim$8 students were randomly sampled and individually interviewed about the instructional effectiveness and their preference on the instructions. The results of this study are summarized as follows: Significant differences between the control group and experimental group are seen in three components; Attention, relevance, and satisfaction. No significant differences are seen in the attitude of confidence. The weakness of the prescriptions of the ARCS model, are insufficient of strategy for 'confidence'. For overcoming the weaknesses of the prescriptions of the ARCS model, developmental type research is needed.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.15-25
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• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

• Journal of Korean Home Economics Education Association
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• v.23 no.3
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• pp.161-183
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• 2011

This study aims to design, develop the impact of a high school course in practical problem- focused teaching plan which will enable students to deal with an aging society, and prepare well for the aging by looking at issues the elderly face. This study set a target of analyzing the 2007 revised curriculum manual to develop instructor-led teaching and learning plans for 'Successful aging preparation'. Five common subjects were reframed on a practical problem basis through factor analysis of preliminary research regarding aging education for teenagers and the 2007 revised curriculum and textbooks of Technology Home Economics, and Human Development. The practical problem was 'What do we need to do to Successfully live an independent life in aging?', and the subjects studied to answer this question were the aging society and population changes. the nature of the elderly, aging preparation, care of the elderly, and welfare services for the elderly. These five subjects were grouped under the main categories of The Aging Society. Understanding the Elderly, and aging Preparation. The ultimate objective of the lessons was, through critical reasoning, to inquire into the causes of current problems the elderly face so that teenagers can understand aging societies and the elderly, and prepare for a Successful aging. Another objective was to seek reasonable alternatives for teenagers as they prepare for Successful and independent aging, and increase their problem-solving abilities in choosing the best course of action by considering the ripple effect of consequences of each of those alternatives. The practical problem-teaching lesson plans consisted of five classes on practical reasoning instruction. This study suggests that new high school curricula should include lessons on preparation for aging so that students can deal successfully with our aging society.