• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of Engineering Education Research
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• v.26 no.1
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• pp.3-11
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• 2023

The purpose of this study is to develop Raspberry Pi-based CanSat instruction materials for liberal arts classes to be used in university space education. The educational satellite simulation program is developed by applying the ADDIE program consisting of analysis, design, development, execution, and evaluation of 15 lessons per semester. The usefulness of the instruction materials is evaluated by a validity test of a total of 6 experts. The proposed materials are applied to 100 college students from various majors. To analyze the impact on creative problem-solving ability, a questionnaire is conducted before and after class, and as a result, it is confirmed that there is a significant improvement in all areas after class. The class satisfaction survey is conducted for a total of 10 questions, and the average score is 4.41 out of 5, which is high. In conclusion, the proposed instruction materials make it possible to achieve successful space education using Raspberry Pi and improve creative problem-solving ability in universities.

• Korean Institute of Interior Design Journal
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• v.14 no.2 s.49
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• pp.206-216
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• 2005

The purpose of this study is a development of $teaching{\cdot}learning$ program based on interior design WBI. WBI's meaning is Web Based Instruction. There can be several procedures that should be designed at the first step: Analyzing, Designing, Building, Testing, Recycling. These stages are constructed based on the theory of procedure about the computer and the $teaching{\cdot}learning$. Each stage is presented the contents of development, the contents of main, the method advantages and problem solving. These procedures and contents of development are the research method simultaneously with the result. Upon the completion of the system, it should undergo the same process continuously so that it can improve over a period of time, contribute to the interior design of students. In addition continuously repetitive requirements pop up in the phase. And it is necessary for this program try to map out a strategy developing and a policy support from university. It's very important that develop the contents of interior design from professor, students and field professor.

• 대한공업교육학회지
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• v.44 no.2
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• pp.1-27
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• 2019

In recent years, space planning ability using 3D sketch software is required in the working field of interior design. However, vocational high school do not respond appropriately to changes in the industry, because the class of vocational high school consists of hands-on practical classes and 2D CAD based classes. There is a shortage of 3D sketch software-based instruction programs that can improve students' spatial planning skills. Therefore, this study is to develop instruction program using 3D sketch software for 'Planning for Residential Space' unit of NCS-based on interior design subject and to find out the effect on students' academic achievement by applying to vocational high school class. The 3d sketch software based instructional program developed in this study was developed through four stages of preparation, development, implementation and evaluation according to the PDIE model process. The experimental design model used nonequivalent group posttest-only design in this study. Experiments were conducted on vocational high school students in construction and 9 hours of interior design subjects were applied. After the experiments, students were tested for academic achievement in the cognitive, affective, and psychomotor areas. As a result, the instruction program using the 3d sketch program developed in this study was found to be more effective in improving students' academic achievement than existing manual instruction program in both cognitive, affective, and psychomotor areas.

• Journal of Korean Library and Information Science Society
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• v.32 no.2
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• pp.165-185
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• 2001

This study measured whether web-based library user education represent web-based instruction theories in education. 9 criteria used were course-related instruction, collaborative learning, evaluation of tutorials, education of information retrieval, contents tables, multimedia interaction between users and librarians, navigational aids, variation of menus. The result showed that both contents and design of web sites were important for good web-based library user education.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.12
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• pp.441-449
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• 1983

Recently, various kinds of computers with architecture different from the usual type of Neumann and Data flow machine have been studied for inproving computational speed. Among them, Feed Forward Computer(F.F.C.) has been remarkably developed. F.F.C. is a computer different from usual digital one in operating system. The usual computer executes operation and operand Fetch after executing instruction fetch and instruction decode. But conceptually, F.F.C. excutes instruction fetch, instruction decode operand fetch and combinational execution simultaneously. Accordingly, a suitable software is needed to operate high reliability and efficiency of this F.F.C. system. In this study, I aim at developing characteristics on highly reliable computer system which should be a blueprint of F.F.C. system in the future.

• Journal of the Korean Society for information Management
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• v.20 no.1
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• pp.121-144
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• 2003

This thesis has a research focus in effectively Practicing cooperative instruction where teacher-librarians play a role. The cooperative Instruction means to practice cooperatively with the subject teachers and teacher-librarians, in teaching subject matters(Korean, English, Social studies. Science, History, and so forth), using the school library. This thesis presents three steps by theory-model-support for a practice method through developing a cooperative instruction model. This is based on curriculum which is an axis of school education and an instructional design theory which is a base theory for subject matters.

• Research in Mathematical Education
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• v.9 no.1 s.21
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• pp.1-9
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• 2005

This paper investigates instructional strategies with potential for improving students' achievement in word problem solving. This review compares and analyzes the direct instruction (DI) and cognitively guided instruction (CGI) research on K-3 word problem solving mathematics students in a demonstration of my position that teachers need to understand student mathematical thinking to enhance students' achievement in word problem solving. CGI provides a more appropriate instructional model than DI for teaching word problem solving. For example, student-centered, conceptual understanding, and children's informal or invented problem solving strategies communicating with each other mathematically, etc. Korean teachers and teacher educators need to consider implementing CGI teaching strategies.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.423-428
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• 2010

In the initial design phase of superscalar microprocessors, a performance model is necessary. A theoretic performance model is very useful since performance for various architecture parameters can be obtained by simply computing equations, without repeating simulations, Previous studies established theoretic performance models using the relation between the instruction window size and the issue width, with the penalties due to branch mispredictions and cache misses. However, the study was intended for unlimited number of functional units, which is insufficient for the real case application. This paper proposes a superscalar microprocessor theoretical performance model which also works for the limited functional units. To enhance the accuracy of our limited functional unit model, instruction dependency rates are employed. By using trace-driven data of SPEC 2000 integer programs as input, this paper shows that the theoretically computed performance of superscalar microprocessor with limited number of functional units is quite similar to the measured performance.