• 대한한의학원전학회지
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• 제27권3호
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• pp.167-182
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• 2014

Objectives : In this article, an analysis of the changing theory(從化理論) of Sameumsamyang(三陰三陽) and Pyobonjung(標本中) in some important medical books, and the historical contexts of those is investigated. Methods : Primary literatures about the changing theory were searched by key words of Sameumsamyang and Pyobonjung in main medical texts, and then analyses and selecting of significant documents have followed. Results : The application of the changing theory to clinical treatment has been mainly done in the process of comprehension and practice about "Sanghanron(傷寒論)". Getting out of simple explanation about meaning of paragraphs in "Sanghanron", the clinical application has been expended to detail drug instruction and prescription managements. Conclusions : The changing theory of Sameumsamyang and Pyobonjung has been actively applied to supporting clinical treatment historically, not recognized merely as a ideal theory.

• 컴퓨터교육학회논문지
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• 제7권2호
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• pp.57-65
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• 2004

e-Learning 에서 교수-학습자들 간에 형성되는 지식들을 체계적으로 관리하여 효과적인 교수 학습을 수행할 목적으로 교수자들이 교수 설계 이론에 따른 다양한 강의틀에 교육 컨텐츠를 보다 쉽게 저작할 수 있는 시스템을 개발하였다. SCORM 표준에 따라 학습객체 간 관계를 설정하여 저작된 컨텐츠는 학습자가 학습내용을 개념화하는데 도움을 줄 것이다. 시맨틱 웹의 RDF를 적용하여 학습객체 간의 관계를 설정함으로써 지식맵을 구성하였고, 교수자가 해당 분야에서 사용되는 단어를 등록하여 일종의 어휘사전을 만들 수 있는 온톨로지를 도입하였다. 학습자의 이해도와 성취도를 고려한 개별학습을 제공하기 위하여 도입된 상호작용점을 따라 학습자마다 개별적인 학습맵이 구성되어 학생 개인의 학습활동과 이해도를 평가할 수 있다.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Progress in Superconductivity
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• 제6권2호
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• 음성과학
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• 제15권2호
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• pp.33-51
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• 2008

Difference of learner speech and loanword phonology is investigated in terms of Korean learners' speech and their loanword adaptation of English words with a post-vocalic word-final stop. When we compared the speech of 12 Korean learners in mid-intermediate level with that of eight English speakers, the learner speech did not reflect loanword phonology of the vowel insertion after a voiced word-final stop (e.g., rib$[\dotplus]$, bad$[\dotplus]$, gag$[\dotplus]$ vs. tip[=], cat[=], book[=]), but, instead, the target phonology of vowel lengthening before a voiced word-final stop (e.g., rib[r.I:b], CAD$[k{\ae}:d]$, bag$[b{\ae}:g]$ vs. rip[rI.p], cat$[k{\ae}t]$, back$[b{\ae}k])$. A longitudinal study of learner speech before and after instruction showed some development toward the acquisition of target phonology. The results indicate that learner speech departs from loanword phonology, and approaches to target speech in a faster rate than direct ratio. Thus, native phonology predicts loanword phonology, but lends little support to learner speech. Our results also indicate that loanword phonology is constant, while learner speech changes toward the acquisition of target phonology.

• Progress in Superconductivity
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• 제7권2호
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1998년도 제13차 학술회의논문집
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• pp.346-351
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• 1998

Cutting process has been automated due to progress of CNC and CAD/CAM, but polishing process has been only depended on experiential knowledge of expert. Polishing work for a curved surface die demands simple and repetitive operations but requires much time for its high precision. Therefore it is operated in the handiwork by skilled worker. However the workers intend to avoid gradually polishing work because of the poor environments such as dust and noise. In order to reduce the polishing time and solve the problem of shortage of skilled workers, it has been done some research for an automation of polishing. To automate the polishing process, a 2 axes polishing robot which is attached to a 3 axes machining center has been developed by our previous research. This automatic polishing robot is able to keep the polishing tool normal on the curved surface of die. Therefore its performance of polishing is improved because of always keeping the tool normal on the surface. In this paper, the smaller sized polishing robot is developed to improve polishing performance. And the controller for 2 axes polishing robot is developed. The controller is composed of TMS320C31 with high speed which is 40-ns instruction cycle time, RAM memory with 64K words, digital input with 64 bits, digital output with 32 bits, and D/A converter with 4 channels, which is 12 bits resolution. To evaluate polishing performance of this developed robot, polishing experiment for shadow mask was carried out.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2003년도 가을 학술발표논문집 Vol.30 No.2 (1)
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• pp.196-198
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• 2003

Virtually every digital signal processors(DSPs) support on-chip multi- memory banks that allow the processor to access multiple words of data from memory in a single instruction cycle. Also, all existing fixed-point DSPs have irregular architecture of heterogeneous register which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multi-memory banks, most of them assumed processors with relatively simple, homogeneous general-purpose resisters. Therefore, several vendor-provided compilers fer DSPs were unable to efficiently assign data to multiple data memory banks. thereby often failing to generate highly optimized code fer their machines. This paper presents an algorithm that helps the compiler to efficiently assign data to multi- memory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly-coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable In quality to the code generated by a coupled approach

• Earthquakes and Structures
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• 제22권1호
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• pp.15-23
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• 2022

One of the key tools in assessing the seismic vulnerability of the structures is the use of fragile functions, which is the possibility of damage from a particular damage surface for several levels of risk from the seismic movements of the earth. The aim of this study is to investigate the effect of two categories of earthquake events on the fragile curve (FRC) of the steel construction system. In this study, the relative lateral displacement of the structures is considered as a damage criterion. The limits set for modifying the relative lateral position in the HAZUS instruction are used to determine the failure modes, which include: slight, moderate, extensive and complete. The results show, as time strong-motion increases, the probability of exceeding (PoE) increases (for Peak ground acceleration (PGA) less than 0.5). The increase in seismic demand increases the probability of exceeding. In other words, it increases the probability of exceeding, if the maximum earthquake acceleration increases. Also, 7-storey model in extensive mode has 20 and 26.5% PoE larger than 5- and 3-storey models, respectively.

• 농촌지도와개발
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• 제21권4호
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• pp.1029-1060
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• 2014

본 연구는 이러닝 환경에서 학습 목표 영역별 콘텐츠 전달 전략에 따른 학습효과와 선호도의 차이 분석을 목적으로 수행되었다. 이를 위해 182명의 고등학교 재학생을 대상으로 세가지 학습 목표영역과 두가지 이러닝 콘텐츠 전달 전략을 제작하여 이러닝 수업을 실시 후 학습효과와 선호도를 측정하였다. 연구결과 인지적 영역과 심동적 영역에서는 이러닝의 전달 전략에 따라 서로 다른 학습효과를 나타냈다. 인지적 영역에서는 학습자 중심형 전달전략이 교수자 중심 전달전략보다 높은 학습효과를 보였으며 심동적 영역에서는 반대로 교수자 중심 전달이 더 높은 학습효과를 나타냈다. 선호도 부분에서도 인지적 영역의 경우 학습자 중심 콘텐츠 전달방식이 교수자 중심보다 학생들이 선호하는 것으로 나타났으며 심동적 영역의 경우는 교수자 중심의 콘텐츠 전달 방식을 더욱 선호하는 것으로 나타났다. 연구결과는 이러닝 설계 시 학습효과와 선호도를 증진시키기 위해서는 프로그램의 학습목표 영역을 고려하여야 한다는 것을 보여주고 있다.