• Journal of Distribution Science
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• v.21 no.7
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• pp.33-40
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• 2023

Purpose: Higher Order Thinking Skills is one of the important aspects in education that must be mastered by the students in order to be qualified in competing at international level. Success in mastering HOTS among the students is always linked to preparation of a good and conducive learning environment. However, does this connection impacts the students' HOTS achievement? Therefore, this research is carried out in order to evaluate the relationship between HOTS and learning environment with the main focus on Accounting Principle Elective Subject (MPEI PP). Research design, data and methodology: Research in the form of correlation is implied in this study and it involves 59 Form 5 students that has learned all syllabus in Form 4's MPEI PP. Results: Evaluation of HOTS level is based on Taxonomy Bloom that covers applying skill, analysing skill, evaluating skill, and creating skill. Result from data analysis found that there is a very weak correlation (r = 0.02) between the two variables with regression equation of average grade point = 75.023 + (-.273) Learning Environment. Conclusion: Thus, a non-significant relationship between HOTS and learning environment is successfully proven through correlation and regression statistical analysis.

• Journal of the Korean Society of Food Culture
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• v.21 no.2
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• pp.154-160
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• 2006

This study examines the service satisfaction rate on high school students(637) in order to provide the basic data for marketing direction by analyzing the importance and satisfaction rate of the service quality. In IPA for the service quality, as the following properties are high in expectation as well as satisfaction they needed to maintain. They are the taste, scent, saltiness, proper temperature of the food, the quantity main food, nutritional value, the degree of freshness, and the smell of dining room. The following properties need the excessive efforts. They are the number of side dishes, eating place, the shape and material quality of dish, the costume of dining workers. As the following showed low importance degrees as well as satisfaction degrees, they don't need concentrated efforts. They are the harmony of color and shape, the interior design of the dining room, the arrangement of tables and chairs, the atmosphere of dining room, and the effect of nutrition instruction. As the education of nutrition is compulsory among the school group meal, the analysis based on the response of questioned students is supposed to be more careful. The items showing low satisfaction degrees while high importance degrees are considered to make an operational plans for the improvement through a variety of menu, the quality of food, the quantity for side-dishes, health control, the cleanness of dishes, the kindness of cooks, the performance of nutritionists, the charge of school meal, and meal time.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.81-86
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• 2023

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.76-81
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• 2024

UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

• International Journal of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.212-220
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• 2024

A recently the advancement of society, AI technology has made significant strides, especially in the fields of computer vision and voice recognition. This study introduces a system that leverages these technologies to recognize users through a camera and relay commands within a vehicle based on voice commands. The system uses the YOLO (You Only Look Once) machine learning algorithm, widely used for object and entity recognition, to identify specific users. For voice command recognition, a machine learning model based on spectrogram voice analysis is employed to identify specific commands. This design aims to enhance security and convenience by preventing unauthorized access to vehicles and IoT devices by anyone other than registered users. We converts camera input data into YOLO system inputs to determine if it is a person, Additionally, it collects voice data through a microphone embedded in the device or computer, converting it into time-domain spectrogram data to be used as input for the voice recognition machine learning system. The input camera image data and voice data undergo inference tasks through pre-trained models, enabling the recognition of simple commands within a limited space based on the inference results. This study demonstrates the feasibility of constructing a device management system within a confined space that enhances security and user convenience through a simple real-time system model. Finally our work aims to provide practical solutions in various application fields, such as smart homes and autonomous vehicles.

• Journal of the Semiconductor & Display Technology
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• v.23 no.3
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• pp.7-13
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• 2024

With the development of technologies such as the Internet of Things (IoT) and autonomous vehicles, research is being conducted on embedded processors that meet high performance, low power, and memory efficiency. The "C" expansion of the RISC-V processor is required to increase memory efficiency. In this paper, we propose an RV32IC processor and compare the benchmark performance score of the RV32I processor with the code size generated by the GCC compiler. In addition, we propose memory access and combination methods to support 16-bit compression commands, and command extension methods. The proposed RV32IC processor satisfies the maximum operating frequency of 50 MHz on the Artix-7 FPGA. The performance was checked using the benchmark programs of the Dhrystone and Coremark, and the code sizes of the RV32I and RV32IC generated by the GCC compiler were compared. The proposed processor RV32IC decreased DMIPS/MHz by 2.72% and Coremark/MHz by 0.61% compared to RV32I, but Coremark's code size decreased by 14.93%.

• Journal of Korean Elementary Science Education
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• v.41 no.4
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• pp.754-770
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• 2022

For teachers, noticing refers to paying attention to something, indicating they interpret it and how they are willing to react to it in the context of their own instruction. Analysis of noticing features enables us to understand the overall characteristics of the teacher's lesson design, practice, and reflection, which are core agents in the educational design and implementation. This can also be taken to be the basis of education design for competency reinforcement for teachers. Therefore, in this study, the characteristics of noticing shown in teachers' reflections after class design and demonstration were identified. For this purpose, the self-reflection journals of 106 elementary pre-service teachers enrolled in the College of Education in Gangwon-do were analyzed. In particular, the journals were gathered that were written after the demonstration dealing with the change of gas volume by temperature in science class. After designing a noticing analysis frame consisting of the five dimensions 'agent', 'stage', 'topic', 'focus', and 'stance', the frequency and ratio of noticing by each dimension's components were derived. The frequency and ratio of noticing for the dimension of 'focus' were analyzed for the dimensions of 'stage' and 'topic'. The results of the study were as follows. For the dimension of 'agent', the frequency of teacher and student was the highest, and for the dimension of 'stage', inquiry activity was the highest. For the 'topic' dimension, class design according to the teaching strategy appeared most frequently, and in the 'focus' dimension, the cases that did not specify the goal of the class and the competencies to be achieved by the students appeared most frequently. In the 'stance' dimension, description showed the highest frequency. From the analysis of how the 'focus' changes according to the 'stage' and 'topic', it was found that a characteristic focus appeared for each component of the dimension. From these results, the implications of the noticing characteristics of pre-service teachers for the design and implementation of teacher education were discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• Journal of The Korean Association of Information Education
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• v.6 no.2
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• pp.163-178
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• 2002

WBI as new instructional method is known to be superior to the traditional face-to-face education method with regard to cost, time and effectiveness of learning. However, WBI lacks the humanity education that teaches human nature such as cooperative spirit or morality, since WBI delivers the knowledge in a mechanical way. The objective of this study is to design and implement Web-based humanity education system that supplements WBI. The system is designed to promote the intimate relation, reliability, and openness between teacher and student. Also, this system encourages the students to experience an affirmative human relation through group activities. In additions, this system promotes parents to join together for improving their understanding of children's learning process.