• Title/Summary/Keyword: Instruction Design

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Hardware Design of VLIW coprocessor for Computer Vision Application (컴퓨터 비전 응용을 위한 VLIW 보조프로세서의 하드웨어 설계)

  • Choi, Byeong-Yoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.9
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    • pp.2189-2196
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    • 2014
  • In this paper, a VLIW(Very Long Instruction Word) vision coprocessor which can efficiently accelerate computer vision algorithm for automotive is designed. The VLIW coprocessor executes four instructions per clock cycle via 8-stage pipelined structure and has 36 integer and floating-point instructions to accelerate computer vision algorithm for pedestrian detection. The processor has about 300-MHz operating frequency and about 210,900 gates under 45nm CMOS technology and its estimated performance is 1.2 GOPS(Giga Operations Per Second). The vision system composed of vision primitive engine and eight VLIW coprocessors can execute pedestrian detection at 25~29 frames per second(FPS). Because the VLIW coprocessor has high detection rate and loosely coupled interface with host processor, it can be efficiently applicable to a wide range of vision applications.

Design and Implementation of Realtime MPEG-2 to MPEG-4 Transcoder (실시간 MPEG-2 to MPEG-4 트랜스코더의 설계 및 구현)

  • Kim Je Woo;Kim Yong-Hwan;Kim Tae-Wan;Choi Beong-Ho
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2003.11a
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    • pp.143-146
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    • 2003
  • 최근 디지털 당송과 이동통신 단말기의 대중화가 이루어짐에 따라 고화질 고해상도의 멀티미디어 컨텐츠의 이동통신 단말기에서의 재생 서비스에 대한 수요가 증가하고 있다 이동통신 단말기에서 멀티미디어 컨텐츠 재생 서비스를 제공하기 위해서는 디지털 방송 컨텐츠를 단말기에 적합한 컨텐츠로 변환할 필요가 있다. 본 논문은 디지털 방송 규격인 MPEG-2 컨텐츠를 이동통신 단말기에서 지원하는 MPEG-4 SP(Simple Profile) 컨텐츠로 실시간으로 변환하는 트랜스 코더에 대한 설계와 구현 기술을 제안한다. 구현된 트래스코더는 화질 유지와 계산량 감소를 위한 적응적 움직임벡터 재구성, 매크로블록 모드 선택, 그리고 움직임벡터 scaling 등의 알고리즘을 포함하고, 인텔사에서 제공하는 SIMD(Single Instruction Multiple Data) 명령어를 이용하여 최적화되었다. 트랜스코더는 30fps, 8Mbps, $720\times480$ 해상도의 멀티미디어 컨텐츠를 다양한 비트율의 30fps, $352\times240$ 해상도의 MPEG-4 컨텐츠로 실시간 변환할 수 있다.

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A Study on SW Development Process for Increasing Computational Thinking (컴퓨팅 사고력 신장을 위한 SW 개발 프로세스 탐구)

  • Yoo, In Hwan
    • KIPS Transactions on Software and Data Engineering
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    • v.5 no.2
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    • pp.51-58
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    • 2016
  • The importance of SW education is being stressed recent days, and the App Inventor is getting attention as a tool of SW education. In this study, I have developed an app Inventor instruction model, which is based on the Design Based Learning and integrated with elements of computational thinking. And I taught the student to apply this model. and then analyzed the app production process and the changes of student. In developing the app, students defined the problem and made a plan to resolve them. And this student had have a sense of accomplishment and self-confidence through practical experience to implement it in their own source code.

Interdisciplinary Knowledge for Teaching: A Model for Epistemic Support in Elementary Classrooms

  • Lilly, Sarah;Chiu, Jennifer L.;McElhaney, Kevin W.
    • Research in Mathematical Education
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    • v.24 no.3
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    • pp.137-173
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    • 2021
  • Research and national standards, such as the Next Generation Science Standards (NGSS) in the United States, promote the development and implementation of K-12 interdisciplinary curricula integrating the disciplines of science, technology, engineering, mathematics, and computer science (STEM+CS). However, little research has explored how teachers provide epistemic support in interdisciplinary contexts or the factors that inform teachers' epistemic support in STEM+CS activities. The goal of this paper is to articulate how interdisciplinary instruction complicates epistemic knowledge and resources needed for teachers' instructional decision-making. Toward these ends, this paper builds upon existing models of teachers' instructional decision-making in individual STEM+CS disciplines to highlight specific challenges and opportunities of interdisciplinary approaches on classroom epistemic supports. First, we offer considerations as to how teachers can provide epistemic support for students to engage in disciplinary practices across mathematics, science, engineering, and computer science. We then support these considerations using examples from our studies in elementary classrooms using integrated STEM+CS curriculum materials. We focus on an elementary school context, as elementary teachers necessarily integrate disciplines as part of their teaching practice when enacting NGSS-aligned curricula. Further, we argue that as STEM+CS interdisciplinary curricula in the form of NGSS-aligned, project-based units become more prevalent in elementary settings, careful attention and support needs to be given to help teachers not only engage their students in disciplinary practices across STEM+CS disciplines, but also to understand why and how these disciplinary practices should be used. Implications include recommendations for the design of professional learning experiences and curriculum materials.

Simulation and Synthesis of RISC-V Processor (RISC-V 프로세서의 모의실행 및 합성)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.1
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    • pp.239-245
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    • 2019
  • RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

Effects of Team-based Problem-based Learning Combined with Smart Education: A Focus on High-risk Newborn Care (스마트 교육을 활용한 팀 기반 문제 중심 학습의 효과: 고위험 신생아 간호를 중심으로)

  • Yang, Sun-Yi
    • Child Health Nursing Research
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    • v.25 no.4
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    • pp.507-517
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    • 2019
  • Purpose: This study was conducted to examine the effects of team-based problem-based learning combined with smart education among nursing students. Methods: A quasi-experimental non-equivalent control group, pre-posttest design was used. The experimental group (n=36) received problem-based learning combined with smart education and lectures 7 times over the course of 7 weeks (100 minutes weekly). Control group (n=34) only received instructor-centered lectures 7 times over the course of 7 weeks (100 minutes weekly). Data were analyzed using the $x^2$ test, the Fisher exact test, and the independent t-test with SPSS for Windows version 21.0. Results: After the intervention, the experimental group reported increased learning motivation (t=2.70, p=.009), problem-solving ability (t=2.25, p=.028), academic self-efficacy (t=4.76, p<.001), self-learning ability (t=2.78, p<.001), and leadership (t=2.78, p=.007) relative to the control group. Conclusion: Team-based problem-based learning combined with smart education and lectures was found to be an effective approach for increasing the learning motivation, problem-solving ability, academic self-efficacy, self-learning ability, and leadership of nursing students.

Design of Electronic Control Unit for Parking Assist System (주차 보조 시스템을 위한 ECU 설계)

  • Choi, Jin-Hyuk;Lee, Seongsoo
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.1172-1175
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    • 2020
  • Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.

Effects of University Students' Social and Teaching Presence on Learning Engagement and Perceived Learning Achievement in Online Courses

  • YUN, Heoncheol;OH, Suna;YOON, Hyunsuk;KIM, Seon
    • Educational Technology International
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    • v.22 no.2
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    • pp.111-137
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    • 2021
  • Embracing the important roles of presence, this study focused on exploring how to enhance online learners' learning engagement and learning achievement in distance higher education settings. More specifically, this study examined the structural relationships among university students' teaching presence, social presence, learning engagement, and perceived learning achievement in online learning environments using structural equation modeling. Data were collected from 206 university students enrolled in online courses in the second semester of 2020 at two large universities. According to the results of the data analysis, there was a significant relationship between teaching and social presence. Teaching presence and social presence predicted learning engagement that positively affected perceived learning achievement. Teaching presence was strongly associated with perceived learning achievement while social presence had a negative impact on that. Additionally, learning engagement had a mediating effect on the relationship between teaching presence and perceived learning achievement. This study found that students who perceived higher levels of teaching and social presences tend to more engage in learning, leading to perceiving better learning achievement. The findings suggest that the design, development, and implementation of effective online instruction should be needed to promote learning engagement, which can be linked to enhancing students' learning achievement. Implications and discussion are addressed in this article.

A Case Study on the Design and Operation of PBL by Employing Blended Learning on Instruction in a Nursing College (간호대학 수업에서 혼합학습을 활용한 문제중심학습 설계 및 운영 사례 연구)

  • Choi, Eun-Young;Lee, Woo-Sook
    • Journal of East-West Nursing Research
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    • v.16 no.2
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    • pp.96-104
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    • 2010
  • Purpose: This research is a case study on a problem-based learning (PBL) model with blended learning in a nursing college. Methods: The target students were nursing sophomores in a nursing college who agreed to participate in a blended learning course and to be subjects in this study for 15 weeks. The questionnaires developed by Baek (2003) and Lee (2007) were modified and applied to collect data. Results: The students' satisfaction with the blending learning was the highest in the item "Online community activities were helpful in enhancing knowledge." The level of satisfaction with PBL was the highest in the item "It was helpful to listen my classmates' opinions rather than thinking all by myself." Conclusion: This study is suggestive that blended learning is effective to improve learning satisfaction by reinforcing practicality of face-to-face study to online learning. Various learning methods based on students' demands and preferences should be applied in nursing education.

A Design and Implementation of 32-bit Five-Stage RISC-V Processor Using FPGA (FPGA를 이용한 32-bit RISC-V 5단계 파이프라인 프로세서 설계 및 구현)

  • Jo, Sangun;Lee, Jonghwan;Kim, Yongwoo
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.4
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    • pp.27-32
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    • 2022
  • RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.