• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.333-336
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• 1999

In this paper, a new high speed parallel input and parallel output GF(2$^{m}$ ) multiplier based on standard basis is proposed. The concept of the multiplication in standard basis coordinates gives an easier VLSI implementation than that of the dual basis. This proposed algorithm and method of implementation of the GF(2$^{m}$ ) multiplication are represented by two kinds of basic cells (which are the generalized and fixed basic cell), and the minimum critical path with pipelined operation. In the case of the generalized basic cell, the proposed multiplier is composed of $m^2$ basic cells where each cell has 2 two input AND gates, 2 two input XOR gates, and 2 one bit latches Specifically, we show that the proposed multiplier has smaller complexity than those proposed in 〔5〕.

• Proceedings of the KSR Conference
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• 2009.05b
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• pp.259-264
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• 2009

This paper proposes a real-time estimation of the boost inductance in a single-phase AC/DC parallel PWM converter for high-speed EMU. The estimation procedure of the boost inductance is only based on the variation of input current and the input AC voltage measurement. The estimated boost inductance is optimized by the least square method. This estimation technique can improve the performance of current controller and reduce the harmonics of the input current in the feed-forward controller. The validity of proposed technique is verified through the MATLAB SIMULINK simulation results.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.290-293
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• 2000

In this paper the algorithm which controls output voltage and power factor independently and the algorithm which controls output voltage with fixed unity power factor are compared and analyzed. These algorithms are applied to single-phase AC/DC parallel are applied to single-phase AC/DC parallel converters for a high speed train system. The control characteristic of the algorithms are compared and analyzed with respect to the output voltage and input power factor when system parameters vary.

• Journal of information and communication convergence engineering
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• v.11 no.4
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• pp.298-306
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• 2013

The scale invariant feature transform (SIFT) is an effective algorithm used in object recognition, panorama stitching, and image matching. However, due to its complexity, real-time processing is difficult to achieve with current software approaches. The increasing availability of parallel computers makes parallelizing these tasks an attractive approach. This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and input/output capabilities of the processor, which results in a system that can perform real-time image and video compression. We apply this implementation to images and measure the effectiveness of such an approach. Experimental simulation results indicate that the proposed method is capable of real-time applications, and the result of our parallel approach is outstanding in terms of the processing performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.6
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• pp.955-961
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• 2017

In this paper, we propose a parallel approximate string matching algorithm with k-mismatches for multiple fixed-length patterns (PMASM) in DNA sequences. PMASM is developed from parallel single pattern approximate string matching algorithms to effectively calculate the Hamming distances for multiple patterns with a fixed-length. In the preprocessing phase of PMASM, all target patterns are binary encoded and stored into a look-up memory. With each input character from the input string, the Hamming distances between a substring and all patterns can be updated at the same time based on the binary encoding information in the look-up memory. Moreover, PMASM adopts graphics processing units (GPUs) to process the data computations in parallel. This paper presents three kinds of PMASM implementation methods in GPUs: thread PMASM, block-thread PMASM, and shared-mem PMASM methods. The shared-mem PMASM method gives an example to effectively make use of the GPU parallel capacity. Moreover, it also exploits special features of the CUDA (Compute Unified Device Architecture) memory structure to optimize the performance. In the experiments with DNA sequences, the proposed PMASM on GPU is 385, 77, and 64 times faster than the traditional naive algorithm, the shift-add algorithm and the single thread PMASM implementation on CPU. With the same NVIDIA GPU model, the performance of the proposed approach is enhanced up to 44% and 21%, compared with the naive, and the shift-add algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

• The KIPS Transactions:PartC
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• v.10C no.7
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• pp.851-856
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• 2003

The LM generator is an improved summation generator with maximum period, near maximum linear complexity and maximum order of correlation immunity, and it has a property with the input-output correlation immunity In this paper, we propose the high-speed m-parallel LM-BSG and 8-parallel LM-BSG for detail as a design example. When compared with a conventional stream cipher, the properties of the proposed cipher exhibited the same crypto-degree (security) with a rt times faster processing.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.3
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• pp.85-90
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• 2015

In this paper, anew parallel event-driven logic simulation is proposed. As the proposed prediction-based parallel event-driven simulation method uses both prediction data and actual data for the input and output values of local simulations executed in parallel, the synchronization overhead and the communication overhead, the major bottleneck of the performance improvement, are greatly reduced. Through the experimentation with multiple designs, we have observed the effectiveness of the proposed approach.

• Journal of Institute of Control, Robotics and Systems
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• v.4 no.3
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• pp.360-371
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• 1998

In this paper, output precision characteristics of a planar 6 degree-of-freedom parallel mechanisms are investigated, where the 6 degree-of-freedom mechanism is formed by adding an additional link along with an actuated joint in each serial subchain of the planar 3 degree-of-freedom parallel mechanism. Kinematic analysis for the parallel mechanism is performed, and its first-order kinematic characteristics are examined via kinematic isotropic index, maximum and minimum input-output velocity transmission ratios of the mechanisms. Based on this analysis, two types of planar 6 degrees-of-freedom parallel manipulators are selected. Then, dynamic characteristics of the two selected planar 6 degree-of-freedom parallel mechanisms, via Frobenius norms of inertia matrix and power modeling array, are investigated to compare the magnitudes of required control efforts of both three large actuators and three small actuators when the link lengths of three additional links are changed. It can be concluded from the analysis results that each of these two planar 6 degrees-of-freedom parallel mechanisms has an excellent control-in-the-small characteristics and therefore, it can be very effectively employed as a high-precision macro-micro manipulator when both its link lengths and locations of small and large actuators are properly chosen.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.69-78
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• 1999

In this paper, direct conversion receiver was designed to even harmonic anti-paralled diode pair ring mixer. Using a second harmonic component of LO instead of LO signal and RF signal are mixed by SHP(Sub Harmonic Pumped) mixer with anti-parallel diode pair. Canceling the harmonics of LO signal in ring mixer, SHP mixer using anti-parallel diode pair could mostly reduce the radiation of LO signal through a input port the most, good isolation characteristic, and low spurious characteristic by LO signal was shown over broad band. The produced SHP mixer showed LO/IF, RF/IF and LO/RF isolation was 24.6dB,36.2dB and 22.5dB respectively. And conversion loss was measured 15.6dB, IF output -35.6dBm with -20dBm RF input and 5.5dBm LO signal. 1dB compression point of If signal, in respect to RF signal, was found at the 0dbm RF signal.