• 대한전기학회논문지:전력기술부문A
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• 제48권2호
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• pp.82-88
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• 1999

In this paper, we propose a new structure optimization method of multilayer neural networks which begin and carry out learning from a bigger network. This method redundant links and neurons according to the rough set theory. In order to find redundant links, we analyze the variations of all weights and output errors in every step of the learning process, and then make the decision table from their variation of weights and output errors. We can find the redundant links from the initial structure by analyzing the decision table using the rough set theory. This enables us to build a structure as compact as possible, and also enables mapping between input and output. We show the validity and effectiveness of the proposed algorithm by applying it to the XOR problem.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.443-447
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• 2001

In this paper, a robust sensorless vector control system for induction motors with a speed estimator and an uncertainty observer is presented. At first, the proposed speed estimator is based on the MRAS(Mode Reference Adaptive System) scheme and constructed with a simple fuzzy logic(FL) approach. The structure of the proposed FL estimator is very simple. The input of the FL is the rotor flux error difference between reference and adjustable model, and the output is the estimated incremental rotor speed Secondly, the unmodeled uncertainties such as parametric uncertainties and external load disturbances are modeled by a radial basis function network(RBFN). In the overal speed control system, the control inputs are composed with a norminal control input and a compensated control input, which are from RBFN observer output and the modeling error of the RBFN, repectively. The compensated control input is derived from Lyapunov unction approach. The simulation results are presented to show the validity of the proposed system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.294-297
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• 2002

We investigate the dynamics of a non-autonomous chaotic oscillator including an optocoupler that shows a periode-doubling and a chaos dynamics under any conditions of input circuit via experiments. Its characteristics was found to coincide input frequency components with output's. But, the relationship between input signals and output signals is different according to the amplitude of driving input voltage and circuit structure. Thus, this result can be applied to a wide variety of optical systems in the future.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.68-68
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• 2000

This paper presents a fuzzy modified PID controller that uses linear fuzzy inference method. In this structure, the proportional and derivative gains vary with the output of the system under control. 2-input PD type fuzzy controller is designed to obtain the varying gains. The proposed fuzzy PID structure maintains the same performance as the general-purpose linear PID controller, and enhances the tracking performance over a wide range of input. Numerical simulations and experimental results show the effectiveness of the fuzzy PID controller in comparison with the conventional PID controller.

• 한국정보통신학회논문지
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• 제21권7호
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• pp.1291-1298
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• 2017

본 논문에서는 무선 통신에서의 높은 전송률과 신뢰도 있는 무선 통신 방안 중 터보 부호를 이용한 MIMO(Multiple Input Multiple Output) 통신 기법과 FTN(Faster Than Nyquist) 기법을 접목시켜 전송률을 향상시키며 신뢰성을 높일 수 있는 복호 방법을 제안한다. 기존의 계층적 시공간 부호화 기반의 MIMO-FTN(Multiple Input Multiple Output-Faster Than Nyquist) 기법은 FTN으로 인한 인접 심볼 간섭을 제거하기 위한 시공간 부호화 방식의 적용으로 전송률의 손해를 초래한다. 이러한 문제점을 해결하기 위해 본 논문에서는 ZF(Zero Forcing) 기법을 이용한 MIMO-FTN 기법에서 ZF 기법의 단점을 보완한 W-ZF(Weighted-Zero Forcing)을 이용한 방식을 제안한다. 본 논문에서는, 시뮬레이션을 통해 계층적 시공간 부호화 기반의 MIMO-FTN 기법과, W-ZF을 적용한 MIMO-FTN 기법, SISO-FTN 기법에서 FTN의 간섭량에 따른 성능과 전송률을 비교 하였다. 그 결과 W-ZF 기법을 적용한 MIMO-FTN 기법이 다른 두 기법보다 전송률에서 2배 더 좋은 것을 확인할 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• 한국멀티미디어학회:학술대회논문집
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• 한국멀티미디어학회 2000년도 춘계학술발표논문집
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.1145-1150
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• 1993

In this paper, two methods of fuzzy modeling are prsented to describe the input-output relationship effectively based on relation characteristics utilizing simplified reasoning and neuro-fuzzy reasoning. The methods of modeling by the simplified reasoning and the neuro-fuzzy reasoning are used when the input-output relation of a system is 'crisp' and 'fuzzy', respectively. The structure and the parameter identification in the modeling method by the simplified reasoning are carried out by means of FCM clustering and the proposed GA hybrid scheme, respectively. The structure and the parameter identification in the modeling method by the neuro-fuzzy reasoning are carried out by means of GA and BP algorithm, respectively. The feasibility of the proposed methods are evaluated through simulation.

• 전력전자학회논문지
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• 제18권1호
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• pp.91-102
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• 2013

This paper proposes the improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source DC-DC converter (Improved LCCT ZSDC) which can generate the bipolar output voltages according to duty ratio D. The proposed converter has the characteristic and structure of Quasi Z-source DC-DC converter(Quasi ZSDC) and conventional LCCT Z-source DC-DC converter(LCCT ZSDC). To confirm the validity of the proposed method, PSIM simulation and a DSP based experiment were performed for each converter. In case which the input DC voltage is 70V, the bipolar output DC voltage of positive 90V and negative 50V could generate. Also, as comparison result of the capacitor voltage ripple in Z-network and the input current under the same condition for each converter, the voltage stress and the capacitor voltage in Z-network of the proposed method were lower compared with the conventional methods. Finally, the efficiency for each method was investigated according to load variation and duty ratio D.