• Proceedings of the KIEE Conference
• /
• 1990.07a
• /
• pp.525-528
• /
• 1990

In this paper, a CMOS Operational Transconductance Amplifier (OTA) which is used for high-frequency operation has been designed and simulated by SPICE 2G program. To increase input linear range, the input stage is designed by cross-coupled pair. And the output stage insert buffer stage for the buffing and gain. The band-width of designed OTA is $50{\sim}60$ [MHz].

• Journal of Korean Institute of Industrial Engineers
• /
• v.22 no.3
• /
• pp.313-324
• /
• 1996

A new policy to determine the waiting position of an idle Automated Guided Vehicle(AGV) is proposed and its performance is compared with the existing waiting position policies. Unlike the existing policies, the queue length in the input buffer is considered in the new policy. As a result, the waiting position based on the new policy depends on the status of the system. The simulation result indicates that the proposed policy reduces the waiting time in both the input and the output buffers significantly, regardless of the number of AGVs in the system. Therefore, the manufacturing lead time can be minimized.

• Journal of IKEEE
• /
• v.14 no.2
• /
• pp.51-57
• /
• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.6
• /
• pp.1085-1094
• /
• 1994

We propose a traffic flow control scheme of B-NT with temporary cell buffering and selective cell discarding to prevent congestion state of the network nodes in B-ISDN systems to reduce or suppress output cell strams towards T interface. We define the states of the network nodes as normal, pre-congestion, and congestion. In a pre-congestion state, the loss-sensitive traffic is temporarily buffered to slow down the rate of the output traffic streams. In a congestion state, the delay-sensitive traffic is selectively discarded to suppress the output traffic streams as possible in addition to the cell buffering. We model the input cell streams and the states of the network nodes with Interrupted Bernoulli Process and 3-state Markov chain to analyze the performance of the proposed scheme in the B-NT system. The appropriate size of the cell buffer is explored by means of simulation and the influence on the performance of the proposed scheme by the network node state is discussed. As results, more than 2,00 cells of buffer size is needed for the control of medium of lower than the medium, degree of congestion occurrence in the network node while the control of high degree of congestion occurrence is nearly impossible.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.1
• /
• pp.149-155
• /
• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.11 no.3
• /
• pp.179-196
• /
• 1986

In this paper, the peformance of a statistical packet voice/data multiplexer is studied. In ths study we assume that in the packet voice/data multiplexer two separate finite queues are used for voice and data traffics, and that voice traffic gets priority over data. For the performance analysis we divide the output link of the multiplexer into a sequence of time slots. The voice signal is modeled as an (M+1) - state Markov process, M being the packet generation period in slots. As for the data traffic, it is modeled by a simple Poisson process. In our discrete time domain analysis, the queueing behavior of voice traffic is little affected by the data traffic since voice signal has priority over data. Therefore, we first analyze the queueing behavior of voice traffic, and then using the result, we study the queueing behavior of data traffic. For the packet voice multiplexer, both inpur state and voice buffer occupancy are formulated by a two-dimensional Markov chain. For the integrated voice/data multiplexer we use a three-dimensional Markov chain that represents the input voice state and the buffer occupancies of voice and data. With these models, the numerical results for the performance have been obtained by the Gauss-Seidel iteration method. The analytical results have been verified by computer simylation. From the results we have found that there exist tradeoffs among the number of voice users, output link capacity, voic queue size and overflow probability for the voice traffic, and also exist tradeoffs among traffic load, data queue size and oveflow probability for the data traffic. Also, there exists a tradeoff between the performance of voice and data traffics for given inpur traffics and link capacity. In addition, it has been found that the average queueing delay of data traffic is longer than the maximum buffer size, when the gain of time assignment speech interpolation(TASI) is more than two and the number of voice users is small.

• Journal of Advanced Navigation Technology
• /
• v.20 no.1
• /
• pp.79-85
• /
• 2016

Network traffic is increased rapidly, due to mobile and social network, such as smartphones and facebook, in recent web environment. In this paper, we improved web response time of existing system using direct buffer of NIO and DMA. This solved the disadvantage of JAVA, such as CPU performance reduction due to the blocking of I/O, garbage collection of buffer. Key values circulated many data due to priority change put on a hash map operated easily and apply a priority modification algorithm. Large response data is separated and stored at a fast direct buffer and improved performance. This paper showed that the proposed method using NIO was much improved performance, in many test situations of cache hit and cache miss.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.22-26
• /
• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Smart Media Journal
• /
• v.4 no.2
• /
• pp.55-61
• /
• 2015

A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.5
• /
• pp.939-948
• /
• 1997

In this paper, we propose the new rate-based transmission rates control algorithm that allocates the fair band-width for ABR service in ATM network. In the traditional ABR service, bandwidth is allocated with constant rate increment or decrement, but in the proposed algorithm, it is allocated fairly to the connected calls by the fuzzy inference of the available bandwidth. The fuzzy inference uses buffer state and the buffer variant rate as the input variables, and uses the total transmission rate as a output variable. This inference a bandwidth is fairly distributed over all ABR calls in service. By simmulation, we showed that the proposed method improved 0.17% in link effectiveness when RIF, RDF is 1/4, 38.6% when RIF, RDF 1/16, and 82.4% when RIF, RDF 1/32 than that of the traditional EFPCA.