• Title/Summary/Keyword: Information Complexity

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Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm

  • Park, Kyeongbin;Chung, Ki-Seok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.2
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    • pp.485-499
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    • 2021
  • Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

On the non-linear combination of the Linear Fedback Shift Register (선형 귀환 쉬프트 레지스터의 비선형적 결합에 관한 연구)

  • Kim, Chul
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.9 no.2
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    • pp.3-12
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    • 1999
  • We introduce feedback registers and definitions of complexity of a register or a sequence generated by it. In the view point of cryptography the linear complexity of an ultimately periodic sequence is important because large one gives an enemy infeasible jobs. We state some results about the linear complexity of sum and product of two LFSRs.

Extended Interactive Hashing Protocol (확장된 Interactive Hashing 프로토콜)

  • 홍도원;장구영;류희수
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.3
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    • pp.95-102
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    • 2002
  • Interactive hashing is a protocol introduced by Naor, Ostrovsk Venkatesan, $Yung^{[1]}$ with t-1 round complexity and $t^2$ - 1 bits communication complexity for given t bits string. In this paper, we propose more efficiently extended interactive hashing protocol with t/m- 1 round complexity and $t^2$/m - m bits communication complexity than NOVY protocol when m is a divisor of t, and prove the security of this.

Enhanced Hybrid XOR-based Artificial Bee Colony Using PSO Algorithm for Energy Efficient Binary Optimization

  • Baguda, Yakubu S.
    • International Journal of Computer Science & Network Security
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    • v.21 no.11
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    • pp.312-320
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    • 2021
  • Increase in computational cost and exhaustive search can lead to more complexity and computational energy. Thus, there is need for effective and efficient scheme to reduce the complexity to achieve optimal energy utilization. This will improve the energy efficiency and enhance the proficiency in terms of the resources needed to achieve convergence. This paper primarily focuses on the development of hybrid swarm intelligence scheme for reducing the computational complexity in binary optimization. In order to reduce the complexity, both artificial bee colony (ABC) and particle swarm optimization (PSO) have been employed to effectively minimize the exhaustive search and increase convergence. First, a new approach using ABC and PSO has been proposed and developed to solve the binary optimization problem. Second, the scout for good quality food sources is accomplished through the deployment of PSO in order to optimally search and explore the best source. Extensive experimental simulations conducted have demonstrate that the proposed scheme outperforms the ABC approaches for reducing complexity and energy consumption in terms of convergence, search and error minimization performance measures.

Matrix Decomposition for Low Computational Complexity in Orthogonal Precoding of N-continuous Schemes for Sidelobe Suppression of OFDM Signals

  • Kawasaki, Hikaru;Matsui, Takahiro;Ohta, Masaya;Yamashita, Katsumi
    • IEIE Transactions on Smart Processing and Computing
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    • v.6 no.2
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    • pp.117-123
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    • 2017
  • N-continuous orthogonal frequency division multiplexing (OFDM) is a precoding method for sidelobe suppression of OFDM signals and seamlessly connects OFDM symbols up to the high-order derivative for sidelobe suppression, which is suitable for suppressing out-of-band radiation. However, it severely degrades the error rate as it increases the continuous derivative order. Two schemes for orthogonal precoding of N-continuous OFDM have been proposed to achieve an ideal error rate while maintaining sidelobe suppression performance; however, the large size of the precoder matrices in both schemes causes very high computational complexity for precoding and decoding. This paper proposes matrix decomposition of precoder matrices with a large size in the orthogonal precoding schemes in order to reduce computational complexity. Numerical experiments show that the proposed method can drastically reduce computational complexity without any performance degradation.

High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture using One's Complement Scheme

  • Kim, Cheolho;Yun, Haram;Ajaz, Sabooh;Lee, Hanho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.3
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    • pp.427-435
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    • 2015
  • This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

Rule of Combination Using Expanded Approximation Algorithm (확장된 근사 알고리즘을 이용한 조합 방법)

  • Moon, Won Sik
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.9 no.3
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    • pp.21-30
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    • 2013
  • Powell-Miller theory is a good method to express or treat incorrect information. But it has limitation that requires too much time to apply to actual situation because computational complexity increases in exponential and functional way. Accordingly, there have been several attempts to reduce computational complexity but side effect followed - certainty factor fell. This study suggested expanded Approximation Algorithm. Expanded Approximation Algorithm is a method to consider both smallest supersets and largest subsets to expand basic space into a space including inverse set and to reduce Approximation error. By using expanded Approximation Algorithm suggested in the study, basic probability assignment function value of subsets was alloted and added to basic probability assignment function value of sets related to the subsets. This made subsets newly created become Approximation more efficiently. As a result, it could be known that certain function value which is based on basic probability assignment function is closely near actual optimal result. And certainty in correctness can be obtained while computational complexity could be reduced. by using Algorithm suggested in the study, exact information necessary for a system can be obtained.

Improved Impossible Differential Attack on 7-round Reduced ARIA-256

  • Shen, Xuan;He, Jun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.11
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    • pp.5773-5784
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    • 2019
  • ARIA is an involutory SPN block cipher. Its block size is 128-bit and the master key sizes are 128/192/256-bit, respectively. Accordingly, they are called ARIA-128/192/256. As we all know, ARIA is a Korean Standard block cipher nowadays. This paper focuses on the security of ARIA against impossible differential attack. We firstly construct a new 4-round impossible differential of ARIA. Furthermore, based on this impossible differential, a new 7-round impossible differential attack on ARIA-256 is proposed in our paper. This attack needs 2118 chosen plaintexts and 2210 7-round encryptions. Comparing with the previous best result, we improve both the data complexity and time complexity. To our knowledge, it is the best impossible differential attack on ARIA-256 so far.

A Hybrid Method on Video Mixing for Multimedia Videoconference

  • Liu, Xin-Gang;Yoo, Kook-Yeol
    • Proceedings of the Korea Information Processing Society Conference
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    • 2005.05a
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    • pp.221-224
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    • 2005
  • In this paper, we propose a fast video mixing method for reducing the computational complexity in the MCU (Multipoint Control Unit) used in the video conferencing. The conventional mixing method is based on the pixeldomain transcoder, of which computational complexity is linearly increased as the number of participants is increased. Basically the method requires N decoders and one huge encoder to mix the bitstreams from the N participants. To reduce the computational complexity, we propose a hybrid mixing method based on the bitstreamdomain and pixel-domain transcoding methods. The proposed method reduces the computational complexity about 45% at the improved quality, compared with the conventional mixing method based on the pixel-domain transcoders.

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Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

  • Jung, Boseok;Kim, Taesung;Lee, Hanho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.488-496
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    • 2016
  • This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.