• Natural Product Sciences
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• v.19 no.4
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• pp.324-328
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• 2013

Soy (Glycine max, family Leguminosae) contains isoflavones and saponins as main constituents. In our preliminary study, soybean ethanol extract (SE) ameliorated scopolamine-induced memory impairment in mice in the passive avoidance task. Therefore, to confirm its ameliorating effect for memory impairments, we measured its effect in scopolamine-induced memory-impaired mice in Morris water maze task. SE significantly prevented scopolamine-induced memory impairment in the Morris water maze task. SE also increased the swimming time within quadrant section of the platform on the day after the final training session test. SE protected the reduction of brain-derived neurotrophic factor (BDNF) expression and cAMP response element-binding protein (CREB) phosphorylation in the hippocampi of scopolamine-treated mice. However, SE did not inhibit acetylcholinesterase. To understand the possible role of soysaponins in memory impairments, we prepared soyasaponins-rich (butanol) fraction of soybean (SRF) and investigated its protective effect against in the passive avoidance and Morris water maze tasks. SRF ameliorated scopolamine-induced memory impairment in mice. The memory impairment-ameliorating effect of SRF was more effective than that of SE. Based on these findings, soybean may improve memory impairment by regulating CREB phosphorylation and BDNF expression.

• Computational Structural Engineering
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• v.4 no.1
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• pp.95-108
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• 1991

An explicit finite element method can be executed more rapidly and effectively on vector computer than on the scalar computer because it has suitable structures for vector processing. In this paper, an efficient vectorization method of the explicit finite element program on the memory-to-memory type vector computer is proposed. First, the general vectorization method which can be applied regardless of the vector architecture is investigated, then the method which is suitable for the memory-to-memory type vector computer is proposed. To illustrate the usefulness of the proposed vectorization method, DYNA3D, the existing explicit finite element program, is migrated on HDS AS/XL V50 which is the memory-to-memory type vector computer. Performance results on actual test show a vector/scalar speedup is above 2.4.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.39-42
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• 2001

This paper proposes the design technique of memory sparing to overcome memory hard error Memory Sparing is used to increase the reliability and availability of commercial, military and space computer such as a Data Server, Communication Server, Flight Computer in airplane and On-Board Computer in spacecraft. But the documents about this technique are rare and hard to find. This paper has some useful information about memory error correction and memory error management.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.184-193
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• 2007

Flash memory adoption in the mobile devices is increasing or vanous multimedia services such as audio, videos, and games. Although the traditional research issues such as out-place update, garbage collection, and wear-leveling are important, the performance, memory usage, and fast mount issues of flash memory file system are becoming much more important than ever because flash memory capacity is rapidly increasing. In this paper, we address the problems of the existing log-based flash memory file systems analytically and propose an efficient log-based file system, which produces higher performance, less memory usage and mount time than the existing log-based file systems. Our ideas are applied to a well-known log-based flash memory file system (YAFFS2) and the performance tests are conducted by comparing our prototype with YAFFS2. The experimental results show that our prototype achieves higher performance, less system memory usage, and faster mounting than YAFFS2, which is better than JFFS2.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.672-674
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• 1998

Java virtual machine has the garbage collector that automate memory management. Mark-compact algorithm is one of the garbage collection algorithm that operating in 2 phases, marking and sweeping. One is Marking is marking live objects reachable from root object set. Sweeping is sweeping unmarked object from memory(return to free memory pool). This algorithm is easy to implement but cause a memory fragmentation. So compacting memory, before memory defragmentation become serious. When compacting memory, all other processes are suspended. It is critical for embedded system that must guarantee real-time processing. This paper introduce enhanced mark-compact garbage collection algorithm. Grouping the objects by their size that minimize memory fragmentation. Then apply smart algorithm to the grouped objects when allocating objects and compacting memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.223-231
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• 2015

As smartphones support a variety of applications and their memory demand keeps increasing, the design of an efficient memory management policy is becoming increasingly important. Meanwhile, as nonvolatile memory (NVM) technologies such as PCM and STT-MRAM have emerged as new memory media of smartphones, characterizing memory references for NVM-based smartphone memory systems is needed. For the deep understanding of memory access features in smartphones, this paper performs comprehensive analysis of memory references for various smartphone applications. We first analyze the temporal locality and frequency of memory reference behaviors to quantify the effects of the two properties with respect to the re-reference likelihood of pages. We also analyze the skewed popularity of memory references and model it as a Zipf-like distribution. We expect that the result of this study will be a good guidance to design an efficient memory management policy for future smartphones.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• Sleep Medicine and Psychophysiology
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• v.5 no.2
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• pp.177-184
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• 1998

Objectives : Disturbance of sleep with or without sleep apnea may impair the memory function. Sleep deficiency, sleepiness, sleep apnea and emotional problem in sleep disorders can induce an impairment of memory function. Methods : In this study, the polysomnographies were administered to 58 sleep apnea patients and 38 sleep disorder patients without sleep apnea. Their clinical symptoms were quantitatively evaluated. Short term and long term memory were evaluated before and after polysom no graphy with Digit symbol test and Rey-Osterrieth complex figure test. And correlations among various sleep, repiratory and clinical variables were statistically studied in order to explore which variables may influence on memory function. Results and Conclusions : Results are as follows. Depth of sleep cis positively correlated with memory function. As sleep apnea increases and average saturation of blood oxygen decreases, memory function is more impaired. Emotional depression, high blood pressure, obesity or alcohol impaired memory function. However, daytime sleepiness was not significantly correlated with memory function. The possible mechanisms how above factors influence on the memory function were discussed.

• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.