• Journal of KIISE:Information Networking
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• v.32 no.4
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• pp.443-451
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• 2005

Stateful inspection devices must maintain flow information. These devices create the flow information also for network attack packets, and it can fatally inflate the dynamic memory allocation on stateful inspection devices under network attacks. The memory inflation leads to memory overflow and subsequent performance degradation. In this paper, we present a guideline to set the flow entry timeout for a stateful inspection device to remove harmful embryonic entries created by network attacks. Considering Transmission Control Protocol (TCP) if utilized by most of these attacks as well as legitimate traffic, we propose a parsimonious memory management guideline based on the design of the TCP and the analysis of real-life Internet traces. In particular, we demonstrate that for all practical purposes one should not reserve memory for an embryonic TCP connection with more than (R+T) seconds of inactivity where R=0, 3, 9 and $1\leqq{T}\leqq{2}$ depending on the load level.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Korean Journal of Biological Psychiatry
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• v.13 no.3
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• pp.191-201
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• 2006

Objectives : The purpose of this study was to investigate whether the cognitive functions would be correlated with psychotic symptoms and whether antipsychotic treatments would affect the cognitive functions after 8 weeks. Methods : The thirty-five schizophrenic patients were conducted in this study. The psychopathology was measured using PANSS. The memory function, executive function, and sustained attention were measured using Memory Assessment Scale(MAS), Wisconsin Card Sorting Test(WCST), and Vigilance(VIG) and Cognitrone(COG) in Vienna Test System. After 8 weeks of antipsychotic treatment, we retested the cognitive tests. Results : 1) The cognitive tests after the 8 week's treatment showed significant improvements in memory and executive function in the schizophrenic patients. On the other side, sustained attention did not show improvement. 2) The change of PANSS were correlated with perseverative response, perseverative error and total correct in WCST at baseline. WCST scores at baseline were correlated with negative symptoms, but not positive ones. Conclusion : These study suggests that 1) the impaired sustained attention could be a vulnerability marker in schizophrenia, 2) memory & executive function deficit could be reversible after treatment, and 3) medication might have a benefit in improving the cognitive functions in schizophrenia. Furthermore, the data supports that the better premorbid executive function was, the more favorable was the treatment response in schizophrenic patients. Finally, this study indicates that executive function might be an index of treatment improvement.

• IMMUNE NETWORK
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• v.5 no.4
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• pp.252-257
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• 2005

Background: This study was designed to investigate the effect of exercise training on defense mechanism of chronic degenerative disease, aging, and memory impairments of senescence-accelerated mouse (SAM)P8 under the hypothesis that "Senile dementia may be prevented by regular exercises". Methods: To evaluate the effects of exercise training on the defense mechanism of aging and memory impairment, SAMP8 were divided into two groups, the control group and exercise training groups. the exercise training group were performed with low $(\dot{V}O_2max\;25{\sim}33%)$, middle ($\dot{V}O_2max$ 50%) and high $(\dot{V}O_2max\;66{\sim}75%)$ intensity exercise. All SAMP8 mice were fed experimental diet ad libitum until 4, 8 months, and dead period. Results: Median lifespan in middle exercise group resulted in a significantly increased (23.5% and 18.7%, respectively), whereas these lifespan in high exercise group resulted in an unexpectedly decreased (13.5% and 12.1%, respectively) compared with control group. Body fat levels in 4 and 8 months of age were significantly decreased 43% to 51% in middle exercise group, whereas were remarkably deceased to 57% in high exercise group compared with control group. It is believed that extended median and maximum lifespan may be effected by calory restriction through the exercise training. Acetylcholine (ACh) levels were significantly increased 6.7% and 8.5% in middle and high exercise groups, and also choline acetyltransfease (ChAT) activities were significantly increased 10.3% and 11.9% in middle and high exercise groups. Conclusion: These results suggest that proper and regular exercises such as middle group ($\dot{V}O_2max$ 50%) may play an effective role in attenuating an oxygen radicals and may play an important role in improving a learning and memory impairments of senile dementia.

• Journal of the Korea Society of Computer and Information
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• v.19 no.7
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• pp.9-16
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• 2014

Since the haze removal algorithm using dark channel prior was introduced, many researches for improving processing speed have been addressed even if it presented impressive results. Remarkable one is using median dark channel prior. Although it has been considered as a very attactive method, processing speed is as low as ever. So, a parallel memory model which is suitable for SIMD architecture processing haze removal on high-definition images in high-speed is introduced in this paper. The proposed parallel memory model allows to access n pixels simultaneously. It is also support stride 3, 5, 7, and 11 in order to execute convolution mask operations, e.g., median filter. The proposed parallel memory model can therefore support enough data bandwidth to process the algorithm using median dark channel prior in high-speed.

• Environmental and Resource Economics Review
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• v.19 no.3
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• pp.485-508
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• 2010

This paper examines the long memory property and investigates cointegration in the dynamics of crude oil markets. For these purposes, we apply the joint ARMA-FIAPARCH model with structural break and the vector error correction model (VECM) to three daily crude oil prices: Brent, Dubai and West Texas Intermediate (WTI). In all crude oil markets, the property of long memory exists in their volatility, and the ARMA-FIAPARCH model adequately captures this long memory property. In addition, the results of the cointegration test and VECM estimation indicate a bi-directional relationship between returns and the conditional variance of crude oil prices. This finding implies that the dynamics of returns affect volatility, and vice versa. These findings can be utilized for improving the understanding of the dynamics of crude oil prices and forecasting market risk for buyers and sellers in crude oil markets.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.101-121
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• 2010

This paper presents an intelligent prefetching technique that significantly improves performance of hybrid fash-disk storage, a combination of flash memory and hard disk. Since flash memory embedded in a hybrid device is much faster than hard disk in terms of I/O operations, it can be utilized as a 'cache' space to improve system performance. The basic strategy for prefetching is to utilize sequential pattern mining, with which we can extract the access patterns of objects from historical access sequences. We use two techniques for enhancing the performance of hybrid storage with prefetching. One of them is to modify a FAST algorithm for mapping the flash memory. The other is to extend the unit of prefetching to a block level as well as a file level for effectively utilizing flash memory space. For evaluating the proposed technique, we perform the experiments using the synthetic data and real UCC data, and prove the usability of our technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.80-88
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• 2002

Visual media(image, graphic, and video) processing poses challenge from several perpectives, specifically from the point of view of real-time implementation and scalability. There have been several approaches to obtain speedups to meet the computing demands in multimedia processing ranging from media processors to special purpose implementations. A variety of parallel processing strategies are adopted in these implementations in order to achieve the required speedups. We have investigated a parallel processing system for improving the processing speed o f visual media related applications. The parallel processing system we proposed is similar to a pipelined memory stystem(MAMS). The multi-access memory system is made up of m memory modules and a memory controller to perform parallel memory access with a variety of combinations of 1${\times}$pq, pq${\times}$1, and p${\times}$q subarray, which improves both cost and complexity of control. Facial recognition, Phong shading, and automatic segmentation of moving object in image sequences are some that have been applied to the parallel processing system and resulted in faithful processing speed. This paper describes the parallel processing systems for the speedup and its utilization to three time-consuming applications.

• Animal cells and systems
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• v.16 no.4
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• pp.302-312
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• 2012

The purpose of this study was to examine whether Phellodendri Cortex extract (PCE) could improve learning and memory impairments caused by lipopolysaccharide (LPS)-induced inflammation in the rat brain. The effect of PCE on modulating pro-inflammatory mediators in the hippocampus and its underlying mechanism were investigated. Injection of LPS into the lateral ventricle caused acute regional inflammation and subsequent deficits in spatial learning ability in the rats. Daily administration of PCE (50, 100, and 200 mg/kg, i.p.) for 21 days markedly improved the LPS-induced learning and memory disabilities in the Morris water maze and passive avoidance test. PCE administration significantly decreased the expression of pro-inflammatory mediators such as tumor necrosis factor-${\alpha}$, interleukin-$1{\beta}$, and cyclooxygenase-2 mRNA in the hippocampus, as assessed by RT-PCR analysis and immunohistochemistry. Together, these findings suggest that PCE significantly attenuated LPS-induced spatial cognitive impairment through inhibiting the expression of pro-inflammatory mediators in the rat brain. These results suggested that PCE may be effective in preventing or slowing the development of neurological disorders, including Alzheimer's disease, by improving cognitive and memory function because of its anti-inflammation activity in the brain.

• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.631-636
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• 2012

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, $Al_2O_3/Y_2O_3/SiO_2$ (AYO) multilayer structures using a high-k $Y_2O_3$ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a $Y_2O_3$ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the $Y_2O_3$ with 4 nm $SiO_2$ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to $10^4$) due to the superior charge-trapping characteristics of $Y_2O_3$. We expect that these high-k $Y_2O_3$ films can be candidates to replace $Si_3N_4$ films as the charge-trapping layer in SONOS-type flash memory devices.