• Title/Summary/Keyword: Implementation loss

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Comparison and Analysis of the Soft-Switching ZVT Converters in Efficiency Using PSPICE (PSPICE를 이용한 소프트 스위칭 ZVT컨버터 효율 비교와 분석)

  • Kim Yoon-Ho;Kim Su-Hong;Lee Kang-Hee;Kim Seung-Mo
    • Proceedings of the KIPE Conference
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    • 2002.07a
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    • pp.364-369
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    • 2002
  • Presently, a high frequency switching technique is used for a converter design to reduce its size and weight. However an increased switching frequency introduces a high switching loss. To the reduce switching loss, soft switching techniques using ZVS and ZCS are applied. It is very important to improve efficiency. However In general to develop new converter circuits, the efficiency and other performance parameters can be determined after design, implementation and experiments. The idea in this paper is to determine and predict efficiency and other operating characteristics without realization and experiments. Thereby a complex design and implementation can be avoided. PSPICE is used as a simulation tool. This is verified by comparing simulation and experiments results of the two different soft switching converters.

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Design and Implementation of Magnetostatic Surface Wave Band Pass Finer at 26GHz Range (26GHz대 정자표면파 대역통과 필터 설계 및 제작)

  • 김명수;김동영;이상석
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.397-400
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    • 2000
  • Telecommunication system demands for increased bandwidths and operating frequencies for analog signal processing could be satisfied in the near future by the emergence of a novel technology based on magnetostatic waves propagating in low loss ferrimagnetic films. The magnetostatic wave is the only available technology for analog signal processing directly at millimeter wave frequencies. This paper has been studied the design and implementation of a Magnetostatic Surface Wave band-pass filter for LMDS system.

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Design, Implementation and Evaluation of Resonant DC/DC Converter Using Low-Profile Magnetic Device (박형 자기소자를 이용한 공진형 직류/직류 컨버터의 설계${\cdot}$제작 및 평가)

  • Ko Jiemyung;Choi Byungcho;Cha Honnyong
    • Proceedings of the KIPE Conference
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    • 2004.07a
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    • pp.350-354
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    • 2004
  • This paper presents theoretical and practical details about the design, implementation, and performance of a series resonant do-to-dc converter using planar magnetics. Result of sinusoidal analysis are used to predict the voltage gain and conversion efficiency. The performance of a prototype converter is presented including the efficiency measurement and theoretical loss breakdown.

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Windowed Quaternion Estimator For Gyroless Spacecraft Attitude Determination

  • Kim, Injung
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.167.5-167
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    • 2001
  • Single point attitude determination method provides an optimal attitude minimizing the Wahba loss function. However, for the insufficient number of measurement vectors, the conventional single point methods has no unique solution. Thus, we introduce the sequential method to and an optimal attitude minimizing the windowed loss function. In this paper, this function is de ned as the sum of square errors for all measurement vectors within the axed sliding window. For simple implementation, the proposed algorithm is rewritten as a recursive form. Moreover, the covariance matrix is derived and expressed as a recursive form. Finally, we apply this algorithm to the attitude determination system with three LOS measurement sensors.

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Loss Optimization for Voltage Stability Enhancement Incorporating UPFC Using Particle Swarm Optimization

  • Kowsalya, M.;Ray, K.K.;Kothari, D.P.
    • Journal of Electrical Engineering and Technology
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    • v.4 no.4
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    • pp.492-498
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    • 2009
  • The placement of the UPFC is the major concern to ensure the full potential of utilization in the transmission network. Voltage stability enhancement with the optimal placement of UPFC using stability index such as modal analysis, Voltage Phasor method is made and the loss minimization including UPFC is formulated as an optimization problem. This paper proposes particle swarm optimization for the exact real power loss minimization including UPFC. The implementation of loss minimization for the optimal location of UPFC was tested with IEEE-14 and IEEE-57 bus system.

Threshold-based Filtering Buffer Management Scheme in a Shared Buffer Packet Switch

  • Yang, Jui-Pin;Liang, Ming-Cheng;Chu, Yuan-Sun
    • Journal of Communications and Networks
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    • v.5 no.1
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    • pp.82-89
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    • 2003
  • In this paper, an efficient threshold-based filtering (TF) buffer management scheme is proposed. The TF is capable of minimizing the overall loss performance and improving the fairness of buffer usage in a shared buffer packet switch. The TF consists of two mechanisms. One mechanism is to classify the output ports as sctive or inactive by comparing their queue lengths with a dedicated buffer allocation factor. The other mechanism is to filter the arrival packets of inactive output ports when the total queue length exceeds a threshold value. A theoretical queuing model of TF is formulated and resolved for the overall packet loss probability. Computer simulations are used to compare the overall loss performance of TF, dynamic threshold (DT), static threshold (ST) and pushout (PO). We find that TF scheme is more robust against dynamic traffic variations than DT and ST. Also, although the over-all loss performance between TF and PO are close to each other, the implementation of TF is much simpler than the PO.

Design and Implementation of the Loss Preventing System using RFID (RFID를 이용한 분실방지 시스템의 설계와 구현)

  • Yong-Hui Lee;Hyun-Gi Kim;Ho-Jeong Song
    • Proceedings of the Korea Information Processing Society Conference
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    • 2008.11a
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    • pp.920-923
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    • 2008
  • We developed the Loss Preventing System using RFID in this paper. This system notifying and knowing that inform loss things from thief to individual precious things. Also, we design and implement to be response from loss thing, and we confirmed stability and proper by real field testing.

COMS DATS Implementation and Test (통신해양기상위성 데이터 송수신 서브시스템의 구축 및 시험)

  • Park, Durk-Jong;Kim, Su-Jin;Ahn, Sang-Il
    • Journal of Astronomy and Space Sciences
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    • v.25 no.4
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    • pp.459-470
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    • 2008
  • DATS which is one of three subsystems of IDACS is responsible to receive Sensor Data, LRIT and HRIT in L-Band and transmit LRIT and HRIT in S-Band from/to COMS satellite. This paper shows detailed test procedures used to verify the performance and functionality of DATS after its implementation was completely finished. As a part of efforts to verify key DATS performance, G/T and EIRP were measured by using solar flux density as radio source. Regarding the verification of DATS functionality, RF loop-back test was conducted to validate if there is no BER degradation excepting MODEM/BB implementation loss occurred in the integrated DATS. Integrated with 13m antenna, DATS successfully restored image from received MTSAT-1R broadcasting data, LRIT and HRIT, of which frequencies are all L-Band. S-Band transmission was also verified through test antenna placed away from 13m antenna by measuring real LRIT and HRIT spectrum in S-Band. From those test results, DATS is determined to be fully ready to communicate with COMS in L-Band and S-Band.

Suboptimal control strategy in structural control implementation

  • Xu, J.Y.;Li, Q.S.;Li, G.Q.;Wu, J.R.;Tang, J.
    • Structural Engineering and Mechanics
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    • v.19 no.1
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    • pp.107-121
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    • 2005
  • The suboptimal control rule is introduced in structural control implementation as an alternative over the optimal control because the optimal control may require large amount of processing time when applied to complex structural control problems. It is well known that any time delay in structural control implementation will cause un-synchronized application of the control forces, which not only reduce the effectiveness of an active control system, but also cause instability of the control system. The effect of time delay on the displacement and acceleration responses of building structures is studied when the suboptimal control rule is adopted. Two examples are given to show the effectiveness of the suboptimal control rule. It is shown through the examples that the present method is easy in implementation and high in efficiency and it can significantly reduce the time delay in structural control implementation without significant loss of performance.

A Low-Power ECC Check Bit Generator Implementation in DRAMs

  • Cha, Sang-Uhn;Lee, Yun-Sang;Yoon, Hong-Il
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.4
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    • pp.252-256
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    • 2006
  • A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.